Patents by Inventor Akira Fukami

Akira Fukami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8133780
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: March 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 8093681
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: January 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Publication number: 20110156155
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Inventors: Shuji IKEDA, Toshiaki YAMANAKA, Kenichi KIKUSHIMA, Shinichiro MITANI, Kazushige SATO, Akira FUKAMI, Masaya IIDA, Akihiro SHIMIZU
  • Publication number: 20110159653
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: March 10, 2011
    Publication date: June 30, 2011
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Publication number: 20110076820
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: September 30, 2010
    Publication date: March 31, 2011
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7910427
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7834420
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Publication number: 20090140349
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 4, 2009
    Inventors: Shuji IKEDA, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7511377
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: March 31, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7456486
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: November 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7397123
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Publication number: 20080099854
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: August 6, 2007
    Publication date: May 1, 2008
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Publication number: 20080073726
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: July 16, 2007
    Publication date: March 27, 2008
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Publication number: 20070241382
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: June 19, 2007
    Publication date: October 18, 2007
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7253051
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: August 7, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Publication number: 20060160297
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: December 9, 2005
    Publication date: July 20, 2006
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7049680
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: May 23, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7023071
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: April 4, 2006
    Assignees: Hitachi Ulsi Engineering Corp., Renesas Technology Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7022568
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: April 4, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Engineering Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Publication number: 20050082622
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Application
    Filed: October 25, 2004
    Publication date: April 21, 2005
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu