Patents by Inventor Akira Kanemasa

Akira Kanemasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4972467
    Abstract: An echo canceller includes a first transversal filter for generating a first echo canceling signal to be canceled from an output signal from a sampler, the first echo canceling signal corresponding to a first sampling value of an echo response waveform of an echo path by a sampling clock when no sampling clock jitter occurs, a second transversal filter for generating a second echo canceling signal corresponding to a difference between the first sampling value and a second sampling value when the sampling clock jitter occurs, two subtractors for canceling the first and second echo canceling signals from a digital reception signal output from the sampler, and a controller for detecting the sampling clock jitter and performing a control operation such that a tap coefficient value of the second filter is added to a tap coefficient value of the first filter to update the tap coefficient value of the first filter, and thereafter, the second echo canceling signal generating operation of the second filter is disabled
    Type: Grant
    Filed: July 20, 1988
    Date of Patent: November 20, 1990
    Assignee: NEC Corporation
    Inventors: Fujio Nakagawa, Akira Kanemasa
  • Patent number: 4965823
    Abstract: An echo canceller of this invention cancels an echo signal input to a sampler through an echo path upon 2-wire/4-wire conversion. The echo canceller includes a filter having a characteristic for reducing a tail of an echo response waveform and inserted between an output terminal of the sampler and a reception output terminal, a first transversal filter for generating a first canceling signal for canceling an echo signal sampled at equal sampling clock intervals after the echo signal passes through the filter, a second transversal filter for canceling a deviation of a sampling value obtained when sampling clock is jittered before the deviation passes through the filter, an enable/disable unit for enabling/disabling a tap output of the second transversal filter, and a controller for, from a moment at which the sampling clock is jittered, controlling the enable/disable unit to cancel a deviation in correspondence with a deviation value of an actual sampling value.
    Type: Grant
    Filed: November 7, 1988
    Date of Patent: October 23, 1990
    Assignee: NEC Corporation
    Inventors: Fujio Nakagawa, Akira Kanemasa
  • Patent number: 4933934
    Abstract: In a time division multiplexing method or device wherein first through N-th-channel samples are extracted at first through M-th unit intervals which correspond to first through M-th bit rates of first through N-th-channel input signals, where M is equal to or less than N, a control signal is produced in response to the input signals to indicate first through M-th consecutive fields in each of successive frames of a time division multiplexed signal and to indicate whether the samples are significant or insignificant samples in each frame. The first through the M-th fields correspond to the unit intervals and have a predetermined total time duration in each frame. The control signal is used moreover to arrange the samples in the fields of each frame by selecting the significant samples with preference to the insignificant samples.
    Type: Grant
    Filed: December 21, 1987
    Date of Patent: June 12, 1990
    Assignee: NEC Corporation
    Inventors: Shinichi Aikoh, Akira Kanemasa
  • Patent number: 4769808
    Abstract: A first difference signal is obtained by subtracting an echo replica from a mixed signal which consists of a received signal and an echo. The echo replica is produced in an adaptive digital filter using an error signal. The first difference signal includes the received signal and a residual echo, and is delayed in a manner to produce a delayed first difference signal. The delayed first difference signal is subtracted from the first difference signal to obtain a second difference signal. Thereafter, a polarity of the residual echo included in said second difference signal is detected. The error signal is obtained based on the detected polarity, and then is applied to the adaptive digital filter.
    Type: Grant
    Filed: September 17, 1985
    Date of Patent: September 6, 1988
    Assignee: NEC Corporation
    Inventors: Akira Kanemasa, Akihiko Sugiyama
  • Patent number: 4730343
    Abstract: An improved decision feedback equalizer, which removes intersymbol interference from pulse transmissions having a desired period, includes an arithmetic circuit (9) for extracting a residual intersymbol interference signal from a residual signal and a delayed residual signal which is produced by delaying the residual signal. The residual signal is produced by a subtractor circuit (2) which subtracts an estimated intersymbol interference signal from the pulse transmissions. A pattern detector circuit (11) is also provided to detect a particular consecutive pattern from a demodulated data sequence produced by a decision or detection circuit (3) for demodulating the residual signal. The residual intersymbol interference signal and a reference signal are inputted to a selector (10) responsive to the output of the pattern detector circuit.
    Type: Grant
    Filed: August 28, 1986
    Date of Patent: March 8, 1988
    Assignee: NEC Corporation
    Inventors: Akira Kanemasa, Akihiko Sugiyama
  • Patent number: 4707824
    Abstract: A method and apparatus cancels an echo by using an echo replica generated such that a tap coefficient of an adaptive filter is sequentially updated, the echo being received from a transmitting end to a four-wire side through a two/four wire converter and being obtained such that a pulse signal having positive and negative polarities is fed into a receiving end, wherein a difference signal (error signal) between the echo replica and a reception signal is calculated; a correlation value between a signal representing a polarity of the error signal and a signal representing a polarity of the echo replica is calculated; when the correlation value is smaller than a predetermined value, a first of two types of tap coefficients which belong to each of a plurality of taps is updated based on at least the error signal and is set as the tap coefficient of the adaptive filter during a period in which the pulse signal is set in the positive polarity, and a second type of tap coefficient is updated based on at least the er
    Type: Grant
    Filed: December 10, 1984
    Date of Patent: November 17, 1987
    Assignee: NEC Corporation
    Inventor: Akira Kanemasa
  • Patent number: 4621172
    Abstract: An echo canceller for cancelling echoes which result from impedance mismatching in a two-wire/four-wire conversion circuit. The prior art employed an input terminal, an output terminal, a transmitter section, a receiver section, a digital-to-analog converter, an adaptive digital filter, a subtractor, a sample hold circuit, an analog-to-digital converter, a multiplier, a low pass filter, a hybrid circuit, and a two-wire communication path, for the purpose of generating a replica of the echo signal to cancel such echos. A method has also been proposed which employs a polarity discriminator circuit instead of an analog-to-digital converter, and utilizes approximation algorithms to correct an adaptive digital filter tap coefficient using the signs of an error signal.
    Type: Grant
    Filed: December 19, 1983
    Date of Patent: November 4, 1986
    Assignee: NEC Corporation
    Inventors: Akira Kanemasa, Kunihiko Niwa
  • Patent number: 4605826
    Abstract: An echo canceler performs convergence in a multiple step manner using a plurality of adaptive digital filters. The adaptive digital filters are sequentially operated to supply data to the corresponding D/A converters such that the echo signals are sequentially cancelled in a stepwise manner. Random access memories are used to allow a decrease in the required number of bits and thus the dimensions of the memories, hence in the overall circuit, so that a compact LSI echo canceler can be easily obtained.
    Type: Grant
    Filed: June 21, 1983
    Date of Patent: August 12, 1986
    Assignee: NEC Corporation
    Inventor: Akira Kanemasa
  • Patent number: 4407018
    Abstract: A digital signal processor is disclosed suited for LSI fabrication comprising a data input circuit for carrying out scaling on a plurality of serial data supplied through a first external terminal group; a coefficient input circuit for carrying out 2's complement conversion on a plurality of specific data from a plurality of serial data supplied through a second external terminal group; a multiplier circuit for carrying out a plurality of multiplications and additions on data from the data input and coefficient input circuits; and an adder circuit for carrying out a plurality of additions and subtractions as well as overflow detection and correction. Data connections in each of the circuits are altered depending on a combination of logical zeros and ones entered through a fourth external terminal group so that one of a plurality of functional modes is selected.
    Type: Grant
    Filed: April 10, 1981
    Date of Patent: September 27, 1983
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Akira Kanemasa
  • Patent number: 4215415
    Abstract: In a recursive digital filter for dealing with data words given by two's complement representation in a common word format comprising a sign bit, an integer bit, and a predetermined number of fractional bits, an overflow detect and correct circuit is supplied with simultaneously produced sign bits of bit-serial first sum, feedback, and second sum data words and with the integer bit of the second sum data word and detects overflow in the second sum data word to produce, for use in the circuit, an overflow detect pulse indicative of presence or absence of overflow. In either event, the circuit produces an overflow-free data word for use in the filter. When overflow is detected, the circuit produces a polarity decision pulse that decides polarities of the overflow-free bits. Otherwise, the circuit determines the overflow-free bits directly by the corresponding bits of the second sum data word.
    Type: Grant
    Filed: September 19, 1978
    Date of Patent: July 29, 1980
    Assignee: Nippon Electric Company, Ltd.
    Inventors: Akira Kanemasa, Hisashi Sakaguchi