Patents by Inventor Akira Kotabe
Akira Kotabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9572491Abstract: A vital signal measurement system including a plurality of terminals aims to facilitate synchronization of each terminal with respect to other terminals. Each of the plurality of terminals (102) is provided with a first vital signal sensor (201) for measuring a vital signal, a first memory (205) for storing a first data which is based on the vital signal, and a first radio communication unit (206) for communicating with other terminals by radio. The first data is applied with a sequence number corresponding to the first data and the number indicates an order in which the first data is acquired. A first terminal (102b) included in the plurality of terminals performs resetting of the sequence number triggered by the synchronous signal which is received by the first radio communication unit.Type: GrantFiled: September 3, 2012Date of Patent: February 21, 2017Assignee: Hitachi, Ltd.Inventors: Tatsuo Nakagawa, Tomoyuki Ishii, Akira Kotabe
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Patent number: 9361978Abstract: The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series. A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).Type: GrantFiled: September 20, 2012Date of Patent: June 7, 2016Assignee: Hitachi, Ltd.Inventors: Nobuhiro Shiramizu, Satoru Hanzawa, Akira Kotabe
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Publication number: 20150230706Abstract: A vital signal measurement system including a plurality of terminals aims to facilitate synchronization of each terminal with respect to other terminals. Each of the plurality of terminals (102) is provided with a first vital signal sensor (201) for measuring a vital signal, a first memory (205) for storing a first data which is based on the vital signal, and a first radio communication unit (206) for communicating with other terminals by radio. The first data is applied with a sequence number corresponding to the first data and the number indicates an order in which the first data is acquired. A first terminal (102b) included in the plurality of terminals performs resetting of the sequence number triggered by the synchronous signal which is received by the first radio communication unit.Type: ApplicationFiled: September 3, 2012Publication date: August 20, 2015Inventors: Tatsuo Nakagawa, Tomoyuki Ishii, Akira Kotabe
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Publication number: 20150221367Abstract: The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series. A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).Type: ApplicationFiled: September 20, 2012Publication date: August 6, 2015Inventors: Nobuhiro Shiramizu, Satoru Hanzawa, Akira Kotabe
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Patent number: 9099177Abstract: With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.Type: GrantFiled: June 10, 2011Date of Patent: August 4, 2015Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Akira Kotabe, Takashi Kobayashi
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Publication number: 20150137386Abstract: There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.Type: ApplicationFiled: November 14, 2014Publication date: May 21, 2015Applicant: PS4 Luxco S.a.r.l.Inventors: Kazuo ONO, Riichiro TAKEMURA, Takamasa SUZUKI, Kazuhiko KAJIGAYA, Akira KOTABE, Yoshimitsu YANAGAWA
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Patent number: 8976608Abstract: A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.Type: GrantFiled: June 5, 2013Date of Patent: March 10, 2015Assignee: Hitachi, Ltd.Inventors: Goichi Ono, Yusuke Kanno, Akira Kotabe
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Patent number: 8964478Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.Type: GrantFiled: May 23, 2013Date of Patent: February 24, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Shinichi Takayama, Akira Kotabe, Kiyoo Itoh, Tomonori Sekiguchi
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Publication number: 20150041885Abstract: A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.Type: ApplicationFiled: October 24, 2014Publication date: February 12, 2015Inventors: Soichiro Yoshida, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe
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Patent number: 8922025Abstract: There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.Type: GrantFiled: June 10, 2013Date of Patent: December 30, 2014Assignee: PS4 Luxco S.a.r.l.Inventors: Kazuo Ono, Riichiro Takemura, Takamasa Suzuki, Kazuhiko Kajigaya, Akira Kotabe, Yoshimitsu Yanagawa
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Patent number: 8901712Abstract: The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory. A semiconductor memory device according to a first aspect of the present invention includes a variable resistance material layer and a channel layer that are connected in series between a first diffusion layer and a metal wire, thereby separating the metal wire and a channel semiconductor layer. A semiconductor memory device according to a second aspect of the present invention includes a variable resistance material layer electrically connecting channel semiconductor layers opposed to each other in a first direction and electrically connecting channel semiconductor layers adjacent to each other in a second direction, wherein a plurality of the channel semiconductor layers is disposed in the second direction.Type: GrantFiled: March 13, 2013Date of Patent: December 2, 2014Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Akira Kotabe
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Patent number: 8872258Abstract: A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.Type: GrantFiled: January 26, 2012Date of Patent: October 28, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Soichiro Yoshida, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe
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Patent number: 8860476Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.Type: GrantFiled: January 17, 2014Date of Patent: October 14, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
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Publication number: 20140218999Abstract: With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.Type: ApplicationFiled: June 10, 2011Publication date: August 7, 2014Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Akira Kotabe, Takashi Kobayashi
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Publication number: 20140154790Abstract: Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG. 1).Type: ApplicationFiled: May 31, 2011Publication date: June 5, 2014Applicant: HITACHI, LTD.Inventors: Kazuo Ono, Tatsuo Nakagawa, Yoshimitsu Yanagawa, Takayuki Kawahara, Akira Kotabe, Riichiro Takemura
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Publication number: 20140132317Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.Type: ApplicationFiled: January 17, 2014Publication date: May 15, 2014Inventors: Yoshimitsu YANAGAWA, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
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Patent number: 8643413Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.Type: GrantFiled: August 29, 2012Date of Patent: February 4, 2014Inventors: Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
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Patent number: 8638121Abstract: A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.Type: GrantFiled: March 23, 2012Date of Patent: January 28, 2014Inventors: Takamasa Suzuki, Akira Kotabe, Tomonori Sekiguchi, Riichiro Takemura
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Publication number: 20140003116Abstract: A semiconductor device includes first and second global bit lines; first, second, third and fourth sense node; a first sense switch coupled between the first sense node and the first global bit line; a second sense switch coupled between the second sense node and the second global bit line; a third sense switch coupled between the third sense node and the first global bit line; a fourth sense switch coupled between the fourth sense node and the second global bit line; a first sense amplifier including a first terminal coupled to the first sense node and a second terminal coupled to the second sense node; a second sense amplifier including a third terminal coupled to the third sense node and a fourth terminal coupled to the fourth sense node. The first, second, third and fourth terminals respectively have first, second, third and fourth parasitic capacitances substantially equal in capacitance value.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: Elpida Memory, Inc.Inventors: Takenori SATO, Kazuhiko KAJIGAYA, Yoshimitsu YANAGAWA, Tomonori SEKIGUCHI, Akira KOTABE, Satoru AKIYAMA
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Publication number: 20130328187Abstract: There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.Type: ApplicationFiled: June 10, 2013Publication date: December 12, 2013Inventors: Kazuo ONO, Riichiro TAKEMURA, Takamasa SUZUKI, Kazuhiko KAJIGAYA, Akira KOTABE, Yoshimitsu YANAGAWA