Patents by Inventor Akira Matsudaira

Akira Matsudaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10766570
    Abstract: A shifting operation detecting apparatus includes a gearbox and a shift change apparatus. The shift change apparatus includes a shifting operation unit, a shifting operation receiving section, a swing lever and a connecting member. A shift operation detector is disposed between the swing lever in an outer shaft section of the shifting operation receiving section and a gearbox case to directly detect a pivoted state of the shifting operation receiving section, and the connecting member is connected to the swing lever from the gearbox case side.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: September 8, 2020
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Akira Tokito, Naotada Matsudaira, Eisuke Kajihara, Kazumitsu Yamamoto, Tatsuya Ryuzaki, Kosuke Tsunashima, Junya Ono
  • Patent number: 10355007
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiying Costa, Dana Lee, Yanli Zhang, Johann Alsmeier, Yingda Dong, Akira Matsudaira
  • Publication number: 20190187737
    Abstract: There is a need to ensure operations at a predetermined operating frequency when a temperature changes in an operating state. A semiconductor device includes: a bias-applied portion applied with a substrate bias; a temperature sensor to detect a temperature; and a substrate bias generator to apply the bias-applied portion with a substrate bias corresponding to the temperature detected by the temperature sensor. The bias-applied portion, while applied with a substrate bias by the substrate bias generator, shifts between an operating state and a stopped state. The substrate bias generator applies the bias-applied portion with a substrate bias configured so as not to cause an upper limit of an operating frequency for the bias-applied portion to be smaller than a predetermined value under condition of the temperature detected by the temperature sensor.
    Type: Application
    Filed: October 29, 2018
    Publication date: June 20, 2019
    Inventors: Masaharu MATSUDAIRA, Takashi HASE, Akira TANABE, Kazuya UEJIMA
  • Publication number: 20190180672
    Abstract: An electronic device may have a display and a gaze tracking system. The electronic device may display images on the display that have a higher resolution in a portion of the display that overlaps a gaze location than other portions of the display. Timing controller circuitry and column driver circuitry may include interpolation and filter circuitry. The interpolation and filter circuitry may be used to perform nearest neighbor interpolation and two-dimensional spatial filtering on low resolution image data. Display driver circuitry may be configured to load higher resolution data into selected portions of a display. The display driver circuitry may include low and high resolution image data buffers and configurable row driver circuitry. Block enable transistors may be included in a display to allow selected blocks of pixels to be loaded with high resolution image data.
    Type: Application
    Filed: August 15, 2017
    Publication date: June 13, 2019
    Inventors: Ivan Knez, Cheuk Chi Lo, Akira Matsudaira, Chun-Yao Huang, Giovanni Carbone, Paolo Sacchetto, Chaohao Wang, Sheng Zhang, Adam Adjiwibawa
  • Publication number: 20170098655
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Xiying COSTA, Dana LEE, Yanli ZHANG, Johann ALSMEIER, Yingda DONG, Akira MATSUDAIRA
  • Patent number: 9589839
    Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: March 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Ikawa, Kiyohiko Sakakibara, Eisuke Takii, Kengo Kajiwara, Seiji Shimabukuro, Akira Matsudaira, Hiroyuki Ogawa
  • Patent number: 9576971
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: February 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier, Yingda Dong, Akira Matsudaira
  • Patent number: 9552991
    Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: January 24, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akira Matsudaira, James Kai, Yuan Zhang, Vinod Purayath, Donovan Lee
  • Patent number: 9553146
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: January 24, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Matthias Baenninger, Akira Matsudaira, Yao-Sheng Lee, Johann Alsmeier
  • Patent number: 9543139
    Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: January 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akira Matsudaira, Donovan Lee
  • Publication number: 20160163729
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 9, 2016
    Inventors: Yanli ZHANG, Johann ALSMEIER, Yingda DONG, Akira MATSUDAIRA
  • Publication number: 20160163389
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 9, 2016
    Inventors: Yanli ZHANG, Johann ALSMEIER, Yinda DONG, Akira MATSUDAIRA
  • Patent number: 9355727
    Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 31, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Yanli Zhang, Johann Alsmeier, Yinda Dong, Akira Matsudaira
  • Patent number: 9224746
    Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: December 29, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod R. Purayath, James Kai, Donovan Lee, Yuan Zhang, Akira Matsudaira
  • Publication number: 20150357413
    Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Applicant: SanDisk Technologies Inc.
    Inventors: Yanli Zhang, Matthias Baenninger, Akira Matsudaira, Yao-Sheng Lee, Johann Alsmeier
  • Patent number: 9209031
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 8, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Matthias Baenninger, Johann Alsmeier, Akira Matsudaira, Jayavel Pachamuthu
  • Publication number: 20150318295
    Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Applicant: SanDisk Technologies, Inc.
    Inventors: James Kai, Vinod Purayath, Donovan Lee, Akira Matsudaira
  • Publication number: 20150318298
    Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Applicant: SanDisk Technologies, Inc.
    Inventors: Akira Matsudaira, James Kai, Yuan Zhang, Vinod Purayath, Donovan Lee
  • Patent number: 9177808
    Abstract: An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: November 3, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Vinod R. Purayath, James Kai, Donovan Lee, Akira Matsudaira, Yuan Zhang
  • Publication number: 20150287733
    Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 8, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Akira Matsudaira, Donovan Lee