Patents by Inventor Akira Ogawa

Akira Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7898676
    Abstract: An image forming device comprises a tray parameter table in which tray IDs for identifying one or trays of the image forming device and tray parameters for the respective tray IDs are stored in a mutually associated manner. A replacing unit receives an input tray ID and an input tray change parameter specified by an externally supplied printer control protocol, and replaces a tray parameter contained in the tray parameter table and corresponding to a tray ID which is the same as the input tray ID, by the input tray change parameter.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: March 1, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Masaaki Igarashi, Akira Ogawa
  • Publication number: 20110032764
    Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
    Type: Application
    Filed: October 15, 2010
    Publication date: February 10, 2011
    Inventors: Akira Ogawa, Masaru Yano
  • Publication number: 20100290291
    Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
    Type: Application
    Filed: June 18, 2010
    Publication date: November 18, 2010
    Inventors: Akira Ogawa, Masaru Yano
  • Publication number: 20100228173
    Abstract: An elastic metal strip 10 aligning the longitudinal direction with the rolling direction of a cold-rolled plate is collected and processed to a shape comprising a correction plate 16 with the longitudinal direction of the elastic metal 10 as the width direction of nail and a plurality of tongue strips 11 protruded from the edge of the correction plate 16 near the nail tip. The tongue strip 11 is folded and bent to form a hooked claw 17 with a double structure of a folding part 18 and a bending part 19. A nail tip 21 of a deformed nail 20 is inserted between the hooked claw 17 and the correction plate 16 to apply a restoring force of elasticity in the correction plate to the deformed nail 20 as correction ability for deformed nails. A wrought wire rod can be used instead of a cold-rolled plate and a Cu—Al—Mn type shape-memory alloy may further be used as a raw material.
    Type: Application
    Filed: December 20, 2006
    Publication date: September 9, 2010
    Inventors: Kiyohito Ishida, Kiyoshi Yamauchi, Ryosuke Kainuma, Yuji Sutou, Toshihiro Omori, Akira Ogawa
  • Patent number: 7729169
    Abstract: Structures, methods, and systems for multiple programming of spare memory region for nonvolatile memory are disclosed. In one embodiment, a nonvolatile memory system comprises a main memory cell array, a spare memory cell array, and a memory controller that divides the spare memory cell array into at least a first region and a second region. The system further comprises a selection module for selecting the main memory cell array and the first region to write data and the first reference cell to write first reference data associated with the data during an initial data writing operation and for selecting the second region to write additional data and the second reference cell to write second reference data associated with the additional data during an additional data writing operation.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: June 1, 2010
    Assignee: Spansion LLC
    Inventors: Masaru Yano, Akira Ogawa
  • Patent number: 7702413
    Abstract: The present invention provides a solution for interleaving data frames, in a semiconductor device manufacturing system in which the processing apparatus for conducting a process on any one of a semiconductor substrate and a thin film on a surface thereof; a self-diagnostic system for diagnosing a state of the processing apparatus; and a parameter fitting apparatus for maintaining a parameter of the self-diagnostic system when an inspection result of the semiconductor substrate having undergone the process has been determined to be correct, and for changing the parameter of the self-diagnostic system when the inspection result has been determined to be incorrect.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: April 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Ushiku, Akira Ogawa, Hidenori Kakinuma, Shunji Shuto, Masahiro Abe, Tatsuo Akiyama, Shigeru Komatsu
  • Publication number: 20100000365
    Abstract: A legged robot that ensures a large step length while keeping the height of the trunk low is realized. The legged robot is provided with a trunk, a pair of legs, and a pair of sliding joints. Each of the sliding joints links one end of each of the legs to the trunk so as to slide in a front and rear direction with respect to the trunk. For each step, one leg is caused to slide forward, and the other leg is caused to slide backward. It is possible to ensure a predetermined distance between the end portion of the one leg and the end portion of the other leg. The legged robot can make the step length large by an amount that is equivalent to this distance irrespective of the length of the legs.
    Type: Application
    Filed: January 11, 2007
    Publication date: January 7, 2010
    Inventor: Akira Ogawa
  • Publication number: 20090290425
    Abstract: The present invention provides a semiconductor memory and a control method therefore, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
    Type: Application
    Filed: July 30, 2009
    Publication date: November 26, 2009
    Inventors: Akira Ogawa, Masaru Yano
  • Patent number: 7623937
    Abstract: The present invention provides a solution for interleaving data frames, in a semiconductor device manufacturing system in which the processing apparatus for conducting a process on any one of a semiconductor substrate and a thin film on a surface thereof; a self-diagnostic system for diagnosing a state of the processing apparatus; and a parameter fitting apparatus for maintaining a parameter of the self-diagnostic system when an inspection result of the semiconductor substrate having undergone the process has been determined to be correct, and for changing the parameter of the self-diagnostic system when the inspection result has been determined to be incorrect.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: November 24, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Ushiku, Akira Ogawa, Hidenori Kakinuma, Shunji Shuto, Masahiro Abe, Tatsuo Akiyama, Shigeru Komatsu
  • Publication number: 20090285019
    Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
    Type: Application
    Filed: July 30, 2009
    Publication date: November 19, 2009
    Inventors: Akira Ogawa, Masaru Yano
  • Publication number: 20090260472
    Abstract: A legged robot is provided whose trunk link is not prone to wobble in the front-back direction during walking. The legged robot is equipped with a trunk link and a pair of legs. Each leg has a pitch joint capable of rotating the connected links in a plane that intersects with a line extending in a lateral direction of the robot. Rotation centers of the pitch joints are located above a center of gravity of the trunk link. The legged robot walks mainly by swinging the legs backward and forward around such rotation centers. Hence, the trunk link wobbles mainly in the front-back direction around the rotation centers as the robot walks. Because the center of gravity of the trunk link is located below the rotation centers, the gravitational force acting on the trunk link acts in a direction to suppress swinging of the trunk link during walking. Due to this, the trunk link of the legged robot is not prone to wobble in the front-back direction during walking.
    Type: Application
    Filed: July 27, 2007
    Publication date: October 22, 2009
    Inventors: Keisuke Suga, Akira Ogawa
  • Patent number: 7596032
    Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: September 29, 2009
    Assignee: Sapnsion LLC
    Inventors: Akira Ogawa, Masaru Yano
  • Publication number: 20090129147
    Abstract: Structures, methods, and systems for multiple programming of spare memory region for nonvolatile memory are disclosed. In one embodiment, a nonvolatile memory system comprises a main memory cell array, a spare memory cell array, and a memory controller that divides the spare memory cell array into at least a first region and a second region. The system further comprises a selection module for selecting the main memory cell array and the first region to write data and the first reference cell to write first reference data associated with the data during an initial data writing operation and for selecting the second region to write additional data and the second reference cell to write second reference data associated with the additional data during an additional data writing operation.
    Type: Application
    Filed: May 23, 2008
    Publication date: May 21, 2009
    Inventors: Masaru YANO, Akira OGAWA
  • Patent number: 7462262
    Abstract: A vertical multitubular heat exchanger that can prevent clogging of a polymerized material and is continuously operable for an extended period of time is provided. The vertical multitubular heat exchanger (1) of the present invention introduces a process fluid containing an easily-polymerizable substance into heat exchanger tubes (28) to perform heat exchange. The vertical multitubular heat exchanger (1) includes a shell (2) extending in a vertical direction, an upper tube sheet (8) and a lower tube sheet (10) respectively disposed at the upper portion (4) and the lower portion (6) of the shell (2), and a plurality of heat exchanger tubes (28) whose outer circumferences (26) of both ends are respectively fixed to the upper tube sheet (8) and the lower tube sheet (10). An upper surface (34) of the upper tube sheet (8) is formed to be sloped and at least one of the heat exchanger tubes (28) is disposed in the vicinity of the lowest position of the upper surface (34) of the upper tube sheet (8).
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: December 9, 2008
    Assignee: Mitsubishi Rayon Co., Ltd.
    Inventors: Tomomichi Hino, Akira Ogawa, Shigetoshi Shimauchi, Toshihiro Sato, Yasuhiro Kabu
  • Patent number: 7463941
    Abstract: A quality control system has: a QC value storage unit, a data acquisition device, a device internal information storage unit, a recipe storage unit, a QC value prediction unit, a wafer determination unit, a recipe selection unit, and a measurement device.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: December 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Ogawa, Yukihiro Ushiku, Tomomi Ino
  • Patent number: 7450419
    Abstract: The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array, comparing the number of bits with a predetermined number of bits, inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits, and programming the inversion data into the memory cell array. The method further includes detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: November 11, 2008
    Assignee: Spansion LLC
    Inventors: Mototada Sakashita, Masaru Yano, Akira Ogawa, Tsutomu Nakai
  • Patent number: 7411086
    Abstract: The present invention is to provide a method of producing an N-alkylaminoalkyl (meth)acrylate containing a small amount of low boiling components, especially, containing a small amount of raw components, without any complicated operations or special apparatuses. The method of producing an N-alkylaminoalkyl (meth)acrylate comprising the steps of: (A) performing the reaction between the (meth)acrylic acid ester and the N-alkylaminoalkyl alcohol in a presence of a catalyst to obtain a reaction solution containing the N-alkylaminoalkyl (meth)acrylate; (B) distilling out components which have lower boiling points than the N-alkylaminoalkyl (meth)acrylate from the reaction solution obtained by the step (A); and (C) distilling the N-alkylaminoalkyl (meth)acrylate; and further comprising the step of: (D) adjusting water concentration at a range from 0.01 to 1 wt %. in the reaction solution which is located after the step (A) and before the step (C).
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: August 12, 2008
    Assignee: Dia-Nitrix Co., Ltd.
    Inventors: Shuhei Otsuka, Akira Ogawa, Tohru Endoh, Shingo Tanaka
  • Patent number: 7372743
    Abstract: A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge accumulation operation is performed, as a preset operation in the initialization operation, on second trapping regions of first and second dynamic reference cells to a charge accumulation operation on a second trapping region of the memory cell. In addition, at the time of data rewrite, preprogram verification and preprogramming are performed on the first trapping regions. This makes it possible to shorten the time taken for initialization and data rewrite.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: May 13, 2008
    Assignee: Spansion, LLC
    Inventors: Masaru Yano, Hideki Arakawa, Mototada Sakashita, Akira Ogawa, Yoshiaki Shinmura, Hajime Aoki
  • Patent number: 7366505
    Abstract: A mobile information terminal receives the delivery of a message from a message delivery server that generates messages that indicate identifiers for mobile applications and processing commands executed by the mobile applications. In one embodiment, a mobile service driver receives a message sent from the message delivery server; a push driver control unit receives the message reception notification from the message service driver and notifies message receiving units that have been registered in advance for message notification about the message reception. The message receiving unit notifies relevant mobile applications among the plurality of mobile applications about the received message based on the identifier of the mobile application indicated by the received message, where notification is provided by the push driver control unit.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: April 29, 2008
    Assignee: SAP AG
    Inventors: Yasuharu Kasai, Akira Ogawa, Akihiro Iwaya
  • Publication number: 20080098165
    Abstract: A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.
    Type: Application
    Filed: October 11, 2007
    Publication date: April 24, 2008
    Inventors: Naoharu Shinozaki, Masao Taguchi, Akira Ogawa, Takuo Ito