Patents by Inventor Akira Takashima
Akira Takashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140061764Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. The first gate insulating film is arranged on the semiconductor substrate. The charge storage layer is arranged on the first gate insulating film, and includes aluminum and silicon. The second gate insulating film is arranged on the charge storage layer, and includes aluminum, silicon, and lanthanum. The control gate electrode is arranged on the second gate insulating film.Type: ApplicationFiled: January 25, 2013Publication date: March 6, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira TAKASHIMA, Daisuke MATSUSHITA
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Patent number: 8664632Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.Type: GrantFiled: August 30, 2012Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Shosuke Fujii, Yoshifumi Nishi, Akira Takashima, Takayuki Ishikawa, Hidenori Miyagawa, Takashi Haimoto, Yusuke Arayashiki, Hideki Inokuma
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Publication number: 20140021528Abstract: A semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge<Ltop and Lgate<Ltop”.Type: ApplicationFiled: July 18, 2013Publication date: January 23, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Akira Takashima, Koichi Muraoka
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Publication number: 20140015444Abstract: A lighting device includes a first light source having a first S/P ratio, a second light source having a second S/P ratio that is higher than the first S/P ratio, and a controller configured to performing dimming control of light output from the first and second light sources. The controller performs the dimming control separately on the first and second light sources at least under a snow covered condition.Type: ApplicationFiled: July 11, 2013Publication date: January 16, 2014Inventors: Takashi SAITO, Toshihide MORI, Ayako TSUKITANI, Hiroshi HAMANO, Akira TAKASHIMA, Kensuke YAMAZOE, Kouichi WADA, Yoshinori KARASAWA
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Publication number: 20130328009Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: ApplicationFiled: August 19, 2013Publication date: December 12, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hidenori MIYAGAWA, Shosuke Fujii, Akira Takashima, Daisuke Matsushita
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Publication number: 20130329485Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira TAKASHIMA, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20130328008Abstract: According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.Type: ApplicationFiled: August 15, 2013Publication date: December 12, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hidenori Miyagawa, Akira Takashima, Shosuke Fuji
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Publication number: 20130299851Abstract: A lighting device includes first and second light emission units. The first light emission unit emits light having a relatively low color temperature and a high feeling of contrast index. The second light emission unit emits light having a relatively high S/P ratio, which is the ratio of scotopic luminance to photopic luminance. The first light emission unit illuminates a region located at a vertical upper side of a region illuminated by the second light emission unit.Type: ApplicationFiled: April 24, 2013Publication date: November 14, 2013Applicant: PANASONIC CORPORATIONInventors: Ayako TSUKITANI, Takashi SAITO, Akira TAKASHIMA, Kouichi WADA, Yoshinori KARASAWA, Toshihide MORI, Hiroshi HAMANO, Kensuke YAMAZOE
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Patent number: 8569823Abstract: According to one embodiment, a semiconductor device includes a semiconductor region, a tunnel insulating film provided on the semiconductor region, a charge storage insulating film provided on the tunnel insulating film and having a hafnium oxide including a cubic region, a block insulating film provided on the charge storage insulating film, and a control gate electrode provided on the block insulating film.Type: GrantFiled: September 19, 2011Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Masao Shingu, Shosuke Fujii, Akira Takashima, Daisuke Matsushita, Jun Fujiki, Naoki Yasuda, Yasushi Nakasaki, Koichi Muraoka
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Patent number: 8558301Abstract: There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures.Type: GrantFiled: August 12, 2011Date of Patent: October 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Akira Takashima, Koichi Muraoka
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Publication number: 20130234087Abstract: A non-volatile resistance change device includes a first electrode made of a metallic element, a second electrode, a variable resistance layer formed between the first electrode and the second electrode, first wiring formed on the first electrode on a side opposite to the variable resistance layer, and second wiring formed on the second electrode on a side opposite to the variable resistance layer. If the width of the first wiring is represented as A (nm), the width of the second wiring represented as B (nm), and the distance between the first electrode and the second electrode represented as L0 (nm), the following equation is satisfied: 3 2 ? AB < L 0 ? 6.7 .Type: ApplicationFiled: September 6, 2012Publication date: September 12, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takashi Yamauchi, Yoshifumi Nishi, Jiezhi Chen, Akira Takashima, Minoru Amano
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Publication number: 20130228736Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.Type: ApplicationFiled: August 30, 2012Publication date: September 5, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Daisuke MATSUSHITA, Shosuke Fujii, Yoshifumi Nishi, Akira Takashima, Takayuki Ishikawa, Hidenori Miyagawa, Takashi Haimoto, Yusuke Arayashiki, Hideki Inokuma
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Patent number: 8482053Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.Type: GrantFiled: August 5, 2011Date of Patent: July 9, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Masao Shingu, Koichi Muraoka
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Publication number: 20130056819Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The second insulating layer comprises a stacked structure provided in order of a first lanthanum aluminate layer, a lanthanum aluminum silicate layer and a second lanthanum aluminate layer from the charge storage layer side to the control gate electrode side.Type: ApplicationFiled: March 20, 2012Publication date: March 7, 2013Inventors: Daisuke MATSUSHITA, Akira Takashima
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Patent number: 8355275Abstract: According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C<T-lead<Roff×C and Ron×C<T-trail.Type: GrantFiled: September 22, 2011Date of Patent: January 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Reika Ichihara, Akira Takashima
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Patent number: 8331137Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.Type: GrantFiled: September 16, 2011Date of Patent: December 11, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Reika Ichihara
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Publication number: 20120250394Abstract: According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C<T-lead<Roff×C and Ron×C<T-trail.Type: ApplicationFiled: September 22, 2011Publication date: October 4, 2012Inventors: Reika Ichihara, Akira Takashima
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Publication number: 20120243293Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.Type: ApplicationFiled: September 16, 2011Publication date: September 27, 2012Inventors: Akira TAKASHIMA, Reika Ichihara
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Publication number: 20120243292Abstract: According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0?x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.Type: ApplicationFiled: September 16, 2011Publication date: September 27, 2012Inventors: Akira TAKASHIMA, Daisuke Matsushita, Takashi Yamauchi, Yuuichi Kamimuta, Hidenori Miyagawa
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Publication number: 20120193597Abstract: According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.Type: ApplicationFiled: January 31, 2012Publication date: August 2, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Masao SHINGU, Akira Takashima, Koichi Muraoka