Patents by Inventor Akitaka Soeno

Akitaka Soeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490638
    Abstract: A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 26, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takashi Kuno, Hiroki Tsuma, Satoshi Kuwano, Akitaka Soeno, Toshitaka Kanemaru, Kenta Hashimoto, Noriyuki Kakimoto, Shuji Yoneda
  • Patent number: 10446649
    Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 15, 2019
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomoo Morino, Shoji Mizuno, Yuichi Takeuchi, Akitaka Soeno, Yukihiko Watanabe
  • Publication number: 20180212028
    Abstract: A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 26, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takashi KUNO, Hiroki TSUMA, Satoshi KUWANO, Akitaka SOENO, Toshitaka KANEMARU, Kenta HASHIMOTO, Noriyuki KAKIMOTO, Shuji YONEDA
  • Patent number: 10002951
    Abstract: A semiconductor device may include a trench, a gate insulating film covering the trench, first conductive type carrier-injected regions intermittently appearing along a predetermined direction, a first conductive type drift region continuously present along the predetermined direction, a second conductive type body region filling a gap between the carrier-injected regions as seen along the predetermined direction, and a gate electrode disposed in the trench. A front end surface located on the front surface side of the gate electrode may include a first end surface at a portion of the gate electrode opposing the carrier-injected regions via the gate insulating film, and a second end surface at least a part of a portion of the gate electrode opposing the body region in the gap. The second end surface may be displaced to the rear surface side relative to the first end surface.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: June 19, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Akitaka Soeno
  • Patent number: 9966460
    Abstract: A switching device includes a semiconductor substrate having a first element range and an ineffective range. First trenches extend in a first direction across the first element range and the ineffective range. Second trenches are provided in each inter-trench region within the first element range and are not provided within the ineffective range. A gate electrode is disposed in the trenches. No contact hole is provided in an interlayer insulating film within the ineffective range. The first metal layer covers the interlayer insulating film. The insulating protective film covers a portion of the first metal layer on its outer peripheral side within the ineffective range. The second metal region is in contact with the first metal layer within an opening of the insulating protective film, and is in contact with a side surface of the opening.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: May 8, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Takashi Kuno
  • Patent number: 9947752
    Abstract: A semiconductor device may include a semiconductor substrate, a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 17, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Akitaka Soeno
  • Patent number: 9941273
    Abstract: A semiconductor device includes: a semiconductor substrate including a trench provided in a surface of the semiconductor substrate; a trench electrode provided in the trench; an interlayer insulating film covering a surface of the trench electrode and protruding from the surface of the semiconductor substrate; a Schottky electrode provided on the surface of the semiconductor substrate, provided in a position separated from the interlayer insulating film, and being in Schottky contact with the semiconductor substrate; an embedded electrode provided in a concave portion between the interlayer insulating film and the Schottky electrode and made of a metal different from a metal of the Schottky electrode; and a surface electrode covering the interlayer insulating film, the embedded electrode, and the Schottky electrode.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 10, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Akitaka Soeno
  • Publication number: 20180026109
    Abstract: A semiconductor device may include a semiconductor substrate; a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.
    Type: Application
    Filed: May 22, 2017
    Publication date: January 25, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Akitaka SOENO
  • Patent number: 9865728
    Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 9, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Masaru Senoo, Takashi Kuno, Satoshi Kuwano, Noriyuki Kakimoto, Toshitaka Kanemaru, Kenta Hashimoto, Yuma Kagata
  • Patent number: 9853139
    Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: December 26, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Jun Saito, Akitaka Soeno, Toshimasa Yamamoto, Narumasa Soejima
  • Patent number: 9818860
    Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 14, 2017
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Naohiro Suzuki, Masahiro Sugimoto, Hidefumi Takaya, Akitaka Soeno, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9786746
    Abstract: A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: October 10, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Masaru Senoo
  • Patent number: 9773883
    Abstract: A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: September 26, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Akitaka Soeno, Yuichi Takeuchi, Narumasa Soejima
  • Patent number: 9768287
    Abstract: A switching device includes a semiconductor substrate having a first element range including first trenches for gates, and an ineffective range not including the first trenches. In an interlayer insulating film, a contact hole is provided within the first element range, and a wide contact hole is provided within the inactive range. The first metal layer contacts the semiconductor substrate within the contact hole and the wide contact hole. The insulating protective film covers an outer peripheral side portion of a bottom surface of a second recess which is provided in a surface of the first metal layer above the wide contact hole. A side surface of an opening provided in a portion of the insulating protective film that includes the first element range is disposed in the second recess. The second metal layer contacts the first metal layer and the side surface of the opening.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: September 19, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Takashi Kuno
  • Publication number: 20170263754
    Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.
    Type: Application
    Filed: February 6, 2017
    Publication date: September 14, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka SOENO, Masaru SENOO, Takashi KUNO, Satoshi KUWANO, Noriyuki KAKIMOTO, Toshitaka KANEMARU, Kenta HASHIMOTO, Yuma KAGATA
  • Publication number: 20170263739
    Abstract: A switching device includes a semiconductor substrate having a first element range including first trenches for gates, and an ineffective range not including the first trenches. In an interlayer insulating film, a contact hole is provided within the first element range, and a wide contact hole is provided within the inactive range. The first metal layer contacts the semiconductor substrate within the contact hole and the wide contact hole. The insulating protective film covers an outer peripheral side portion of a bottom surface of a second recess which is provided in a surface of the first metal layer above the wide contact hole. A side surface of an opening provided in a portion of the insulating protective film that includes the first element range is disposed in the second recess. The second metal layer contacts the first metal layer and the side surface of the opening.
    Type: Application
    Filed: February 6, 2017
    Publication date: September 14, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka SOENO, Takashi KUNO
  • Publication number: 20170263738
    Abstract: A switching device includes a semiconductor substrate having a first element range and an ineffective range. First trenches extend in a first direction across the first element range and the ineffective range. Second trenches are provided in each inter-trench region within the first element range and are not provided within the ineffective range. A gate electrode is disposed in the trenches. No contact hole is provided in an interlayer insulating film within the ineffective range. The first metal layer covers the interlayer insulating film. The insulating protective film covers a portion of the first metal layer on its outer peripheral side within the ineffective range. The second metal region is in contact with the first metal layer within an opening of the insulating protective film, and is in contact with a side surface of the opening.
    Type: Application
    Filed: February 6, 2017
    Publication date: September 14, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka SOENO, Takashi KUNO
  • Patent number: 9722075
    Abstract: Described herein is a semiconductor device including a semiconductor substrate in which an element region and a termination region surrounding the element region are provided. The element region includes: a gate trench; a gate insulating film; and a gate electrode. The termination region includes: a plurality of termination trenches provided around the element region; an inner trench insulating layer located inside of each of the plurality of termination trenches; and an upper surface insulating layer located at an upper surface of the semiconductor substrate in the termination region. The upper surface insulating layer includes a first portion and a second portion having a thinner thickness than the first portion and located at a location separated from the element region than the first portion, and a gate wiring is located at an upper surface of the first portion and is not located at an upper surface of the second portion.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 1, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Yuji Fukuoka
  • Publication number: 20170213907
    Abstract: High voltage-resistance of a switching device including a p-type region being in contact with a lower end of a bottom-insulating-layer is realized. The switching device includes a bottom-insulating-layer disposed at a bottom in a trench, and a gate electrode disposed on a front surface side of the bottom-insulating-layer. A semiconductor substrate includes a first n-type and p-type regions being in contact with the gate insulating film, a second p-type region being in contact with an end of the bottom-insulating-layer, and a second n-type region separating the second p-type region from the first p-type region. Distance A from a rear-surface-side-end of the first p-type region to a front-surface-side-end of the second p-type region, and distance B from a rear-surface-side-end of the-bottom-insulating layer to a rear-surface-side-end of the second p-type region satisfy A<4B.
    Type: Application
    Filed: June 3, 2015
    Publication date: July 27, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Akitaka SOENO, Sachiko AOI, Shinichiro MIYAHARA
  • Patent number: 9679997
    Abstract: A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front surface side of the bottom-body region, and a top-body region on a front surface side of the IGBT barrier region. A diode region is include with a bottom-anode region on a front surface side of the diode drift region, a diode barrier region on a front surface side of the bottom-anode region, a top-anode region on a front surface side of the diode barrier region, and a pillar region extending from the front surface of the semiconductor substrate, piercing the top-anode region, and reaching the diode barrier region, and connected to the front surface electrode and the diode barrier region. An impurity concentration of the top-body region is lower than an impurity concentration of the bottom-anode region.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 13, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Akitaka Soeno