Abstract: A fault display module for a hardware device includes an external power input for providing power to the fault display unit when the associated hardware device is disconnected from its power supply.

Abstract: A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.

Abstract: A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.

Abstract: A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.

Abstract: A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units.

Abstract: A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.

Abstract: The disclosed invention relates to a re-synchronization system that operates in a switching arrangement receiving a plurality of incoming data packets. The switching arrangement is made of an active switch card that transmits the incoming data packets and a backup switch card that may be re-activated by an operator after replacement. The re-synchronization system is implemented in each switch card. When the backup switch card is re-activated, both switch cards receive the incoming data packets and the system of the invention allows to re-synchronized both switch cards by controlling the transmission of the incoming data packets out of each switch card until the same data packets are transmitted. The re-synchronization system further comprise storage for storing the incoming data packets and detector for detecting a re-synchronization information among the incoming data packets.

Abstract: A data packet switching node that temporarily stores data packets received from at least one source network adapter and transmits them to at least one destination network adapter comprises a data packet flow control system to control the data packet flow. The data packet flow control system comprises identifier to determine the at least one destination adapter of each received data packet. Then, flow control logic coupled to the storage allow computing a data packet flow value representing the traffic for the at least one destination adapter. The data packet flow value is transmitted simultaneously to the at least one source network adapter and to the at least one destination network adapter each time a data packet for the at least one destination network adapter is stored into the storage.

Abstract: A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing.

Abstract: A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing.

Abstract: A switchover system and method is described. The invention preferably operates in a data packet switching system for transmitting through a switching arrangement data packets that comprise at least a data packet identifier. The switching arrangement comprises at least an active switch card associated to a backup switch card. And the active switch card and the backup switch card receive simultaneously at least a data packet and transmit it to a network adapter device. The switchover system comprises active and backup means for respectively storing at an active and backup data packet address the transmitted at least data packet. It also comprises switchover detecting means coupled to the active and backup storing means for detecting a switchover event, and control means coupled to the active and backup storing means and to the switchover detecting means for setting the backup storing means when a switchover event is detected.

Abstract: A system and method to print graphic documents in booklet format. The system allows the user to have a booklet print option available as a print option of a graphic editor. The system generates a plurality of graphic pages, and orders the pages into logical sequences, each logical sequence being associated to a predefined layout. The ordering of the pages includes ordering the plurality of graphic pages into a booklet logical sequence, where the booklet logical sequence is associated with a booklet layout. The pages are ordered according to the value of a remainder ‘R’ according to ‘R=N_modulo(4)’, wherein ‘N’ is the number of graphic pages to be ordered.

Abstract: A data transmission system comprising a packet switch module interconnecting LAN adapters, a plurality of input and output ports connected to the LAN adapters such that each pair of input and output ports defines a crosspoint within the switch module, and a memory block located at each crosspoint of the switch module for storing at least one data packet. At each clock time, a scheduler causes a data packet stored in a memory block, among all memory blocks corresponding to a given output port, to be transferred to that output port.

Abstract: A computer implemented method to perform an insertion request of new schematic pages within a plurality of numbered schematic pages created with a design schematic capture tool is described. The method allows a user to insert as much as new pages in a user friendly manner by being implemented in a design schematic capture tool through a Graphical User Interface (GUI). The GUI offers a location field to enter the schematic page number where to insert the new pages, a number field to enter the number of new schematic pages to be inserted, and an execution key to be depressed to execute the insertion operation automatically.

Abstract: A security system for preventing unauthorized use of a computer device. An extractable security piece includes an extractable main private key and a main PC public key. A PC security area which is a non-extractable part of the computer device includes a PC private key and an extractable main public key, which, together with the keys of the extractable security piece, constitute a Public Key Infrastructure. The extractable security piece and the PC security area include processing means for mutual authentication of the extractable security piece and the PC security area after the extractable security piece, which had been previously removed, has been reinserted in the computer device, thereby enabling the authorized user to access data stored in the computer device.

Abstract: In a remote computer, a method for providing a file comprises the steps of receiving a request for this file, identifying this file as being stored in a distant server, requesting the distance server to send the file, identifying this file as being used, and forwarding this file. Further, in a local server, a method for transferring a file from a home server comprises the steps of receiving a request for this file, this request comprising the home server identification, checking that this file is not locally stored, requesting this file to the home server, identifying the file as being locally used, and forwarding this file.

Abstract: The invention discloses a method of updating, in nodes on both ends of a secure link, the encryption key they share to encrypt and decrypt data. When having to transmit data from one of the nodes towards its peer remote node, a data base in the forwarding node, is first updated from the data to be transmitted. Then, encryption is performed and data transmitted to the peer remote node while a next-to-use encryption key is derived from the new contents of the data base. When received, data are decrypted with the current value of the encryption key and the peer remote node data base is updated identically from the received decrypted data after which a next-to-use encryption key is derived, thereby obtaining in the peer remote node, a next-to-use identical key. The data base is preferably the dictionary of a data compression/decompression system used simultaneously with encryption/decryption to transmit data over the secure link.

Abstract: Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) comprising at least a packet switch module interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. The system comprises a memory block at each crosspoint of the switch module including memory control means for determining from the header of the received data packet whether the packet is to be forwarded to the output port associated with the crosspoint and a data memory unit for storing at least the data packet into the data memory unit before sending it to the output port.

Abstract: Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) comprising at least a packet switch module interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded.

Abstract: Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. The system comprises a memory block located at each cross point of the switch module for storing any data packet which is received from the input port corresponding to the cross point and which is to be forwarded to the output port corresponding to this cross point, and a scheduler associated with each output port for selecting at each clock time a memory block among all memory blocks corresponding to the output port and causing the memory block to forward the stored data packet to the output port when predetermined criteria are met.