Patents by Inventor Alan A. Hale
Alan A. Hale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8604475Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: September 28, 2012Date of Patent: December 10, 2013Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Patent number: 8525565Abstract: A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.Type: GrantFiled: June 9, 2010Date of Patent: September 3, 2013Assignee: Texas Instruments IncorporatedInventors: Mujibur Rahman, Timothy D. Anderson, Alan Hales
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Publication number: 20130169332Abstract: A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.Type: ApplicationFiled: June 9, 2010Publication date: July 4, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mujibur Rahman, Timothy D. Anderson, Alan Hales
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Patent number: 8397112Abstract: An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.Type: GrantFiled: December 16, 2010Date of Patent: March 12, 2013Assignee: Texas Instruments IncorporatedInventors: Mujibur Rahman, Timothy Anderson, Alan Hales
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Patent number: 8375265Abstract: In an embodiment of the invention, an integrated circuit with several clock domains bank is tested by first disabling a PLL clock and scanning test data into scan chains. Next delay fault testing (DFT) code is transmitted to each distributed clock divider on the integrated circuit. The PLL clock is then enabled to the distributed clock dividers. Selected clock dividers generate launch pulses that allow test data to be propagated from the scan chains into circuit blocks in the clock domains. Capture pulses are then generated by selected distributed clock dividers to capture test data coming form the circuit blocks into the scan chains. Next the PLL clock is disabled and the test data is scanned from the scan chains to an on-chip test control circuit.Type: GrantFiled: September 13, 2011Date of Patent: February 12, 2013Assignee: Texas Instruments IncorporatedInventors: Ramakrishnan Venkatasubramanian, Alan Hales, William Wallace
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Patent number: 8299464Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: October 25, 2010Date of Patent: October 30, 2012Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20120036408Abstract: An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.Type: ApplicationFiled: December 16, 2010Publication date: February 9, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mujibur Rahman, Timothy Anderson, Alan Hales
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Publication number: 20110041019Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: October 25, 2010Publication date: February 17, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee D. Whetsel, Alan Hales
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Patent number: 7842949Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: December 15, 2009Date of Patent: November 30, 2010Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20100157502Abstract: A relay switch decoupler is disclosed. The relay switch decoupler may include a first contact, and a second contact selectively coupled to the first contact. The relay switch decoupler may further include an insulating decoupler situated proximate to the first contact and the second contact. The relay switch decoupler may further include an actuator coupled to the insulating decoupler and configured to cause the insulating decoupler to decouple the first contact from the second contact in response to a control signal.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Inventors: David Alan Hale, Bryan Anthony Lavezzi, Sarah Elizabeth Schonert
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Publication number: 20100095171Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: December 15, 2009Publication date: April 15, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee D. Whetsel, Alan Hales
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Patent number: 7655946Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: December 8, 2008Date of Patent: February 2, 2010Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20090089634Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: December 8, 2008Publication date: April 2, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee D. Whetsel, Alan Hales
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Patent number: 7491970Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: January 9, 2008Date of Patent: February 17, 2009Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Patent number: 7389455Abstract: A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to the input ports of the register file to pre-load the register file to a known state.Type: GrantFiled: May 14, 2006Date of Patent: June 17, 2008Assignee: Texas Instruments IncorporatedInventor: Alan Hales
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Publication number: 20080106287Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: January 9, 2008Publication date: May 8, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Whetsel, Alan Hales
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Publication number: 20070114529Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: January 23, 2007Publication date: May 24, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Whetsel, Alan Hales
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Publication number: 20070061645Abstract: A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to the input ports of the register file to pre-load the register file to a known state.Type: ApplicationFiled: May 14, 2006Publication date: March 15, 2007Applicant: Texas Instruments IncorporatedInventor: Alan Hales
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Patent number: 7183570Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. The response patterns include one of expected data and mask data input on an output pad of the die/IC and the other of expected data and mask data input on another pad of the die/IC, which may be an input pad or an output pad. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: April 11, 2005Date of Patent: February 27, 2007Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20060259838Abstract: A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This invention supplies a predefined pattern to parallel scan chains following power-on reset. These parallel scan chains are already required for structural manufacturing test. Once the power-on reset scanning is complete, the power-on reset sequencer indicates completion of state initialization to other circuits. These other circuits are those which interact with the module or device using this invention.Type: ApplicationFiled: May 4, 2006Publication date: November 16, 2006Inventors: Lewis Nardini, Alan Hales