Abstract: In one form of invention a process of operating a host computer coupled to a communications network including: determining whether a diversity flag is set, when a communications connection is requested; sending a request from the host computer to a proxy identification list server in a communications network for proxy pair identification information, when the diversity flag is set; receiving in the host computer the proxy pair identification information from the proxy identification list server in response to the host request; and wherein the sending includes communicating from the host computer to a destination computer though a first communication path that includes a first proxy device and though a second communication path, separate from the first communication path, that includes the second proxy device.

Abstract: A system includes a plurality of compute modules and a first processor configured to implement a virtualization layer, where the virtualization layer is configured to support real time jobs. The system also includes a hardware support layer coupled between the plurality of compute modules and the virtualization layer, where the hardware support layer is configured to provide an interface between the virtualization layer and the plurality of compute modules.

Abstract: Disclosed herein are a shared memory controller and a method of controlling a shared memory. An embodiment method of controlling a shared memory includes concurrently scanning-in a plurality of read/write commands for respective transactions. Each of the plurality of read/write commands includes respective addresses and respective priorities. Additionally, each of the respective transactions is divisible into at least one beat and at least one of the respective transactions is divisible into multiple beats. The method also includes dividing the plurality of read/write commands into respective beat-level read/write commands and concurrently arbitrating the respective beat-level read/write commands according to the respective addresses and the respective priorities. Concurrently arbitrating yields respective sequences of beat-level read/write commands corresponding to the respective addresses.

Abstract: System and method embodiments are provided for messaging-based System-on-a-chip (SoC) power gating. The embodiments enable fine granularity SoC power gating without introducing significant latency and substantially maximizes SoC power reduction. In an embodiment, a method in a first SoC resource for messaging-based power gating includes receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource; determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource; setting a wake-up time timer to expire at the wake-up time; and waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep.

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: The present invention provides a method of operating a base station transmitter. In one embodiment, the method includes providing a cellular downlink synchronization signal having primary and secondary portions, wherein the primary portion is common for all cells and the secondary portion is cell-specific and transmitting the cellular downlink synchronization signal. In another embodiment, the method includes providing a cellular downlink synchronization signal having primary and secondary portions wherein the primary portion employs a corresponding one of a plurality of different primary signals allocated to adjoining transmission cells. The method also includes further providing cell-specific information in the secondary portion and transmitting the cellular downlink synchronization signal. The present invention also provides a method of operating user equipment.

Abstract: A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver in a first cell (Cell 1). Each of the plurality of frames comprises a bit group (22), and the bit group uniquely distinguishes the first cell from a second cell (Cell 2) adjacent the first cell. The transmitter circuitry further comprises circuitry (54) for inserting a bit sequence into the bit group. The bit sequence is selected from a plurality of bit sequences (S1-SK) such that successive transmissions by the transmitter circuitry comprise a cycle of successive ones of the plurality of bit sequences.

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: An integrated circuit (IC) chip (100) expanded to nerve fiber (602) growth in the third dimension by through-silicon via-holes (TSV) (131), with an electrically conductive inner sidewall (303) having a roughness (303a) suitable for supporting the growing fiber and conductive connections (210) to the circuitry (101). The TSVs are fabricated parallel to each other and may be arrayed in regular patterns. The chip, provided with a pad (230) for contacting a nerve end and attaching a neuron, acts as a permanent protective sheath for the parallel growing fibers. Nerve fiber growth is stimulated by combining in the chip electrical and magnetic pulses and neurotrophic factors (603); continuous communication with external monitors is provided. The IC provides each TSV with a signal generator, electric and magnetic field generator, power source, potential sensor, and transceiver.

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: A communication circuit (28) is designed with a signal processing circuit (370) arranged to produce a first plurality of data signals and receive a second plurality of data signals. A transmit circuit (364) is coupled to receive the first plurality of data signals and transmit each data signal of the first plurality of data signals on a respective transmit frequency in a predetermined sequence of transmit frequencies. A receive circuit (362) is coupled to receive each data signal of the second plurality of data signals from a remote transmitter on the respective transmit frequency in the predetermined sequence. The receive circuit applies the second plurality of data signals to the signal processing circuit.

Abstract: Multipath relative channel estimations for weighting maximal ratio combining of RAKE detectors in wireless communication systems uses maximal eigenvectors of covariance matrices of path signals. Estimates for close-in and outlying sets of symbols provides linear time change channel estimation.

Abstract: An apparatus and method for transmitting and receiving a bit stream. On the transmission side, coded bits (Y.sub.t) and an interleaved version of the coded bits (X.sub.t) are separately modulated and transmitted. On the reception side, a priori output probabilities produced by a probability generator (34) are combined (112) and then input to a SISO decoder (111). Combined a posteriori output probabilities (115) produced by the SISO decoder are split (113) and then fed back to the probability generator.

Abstract: A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver in a first cell (Cell 1). Each of the plurality of frames comprises a bit group (22), and the bit group uniquely distinguishes the first cell from a second cell (Cell 2) adjacent the first cell. The transmitter circuitry further comprises circuitry (54) for inserting a bit sequence into the bit group. The bit sequence is selected from a plurality of bit sequences (S1-SK) such that successive transmissions by the transmitter circuitry comprise a cycle of successive ones of the plurality of bit sequences.

Abstract: The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates.

Abstract: A programmable co-processor system comprising a datapath, a microprogram, and a microcontroller is provided. The datapath includes one or more datapath elements operable to receive input signals. The microprogram memory includes a microprogram operable to control the datapath in order to process the input signals. The microcontroller is operable to modify the microprogram based on a modification command.