Abstract: A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

Abstract: In a wireless communication receiver (31) of a wireless communication system that utilizes transmit diversity and turbo coding, symbol probabilities (45, 46) are generated (34) based at least in part on a posteriori output probabilities (47, 48) produced by SISO decoders (35, 36).

Abstract: A cable modem (20) having a blind equalizer (40) in its equalization function (28) is disclosed. The blind equalizer (40) includes an adaptive equalizer (44) and an approximating update function (42) that provides updated equalization coefficients to the adaptive equalizer (44) using the Constant Modulus Algorithm, wherein the error in the adaptive equalizer output is estimated. The estimates are based upon a determination of the maximum and minimum of the real and i components of symbols output by the adaptive equalizer (44). Efficiency in the computations required for updating the equalizer coefficients is obtained, without sacrificing convergence.

Abstract: A method of controlling the transmission amplitude of signals in a DMT communications system limited by a predefined dynamic range is disclosed. A block of bits is converted to a set of M constellation points in the fourier domain. The M constellation points are then mapped to a set of N complex points, wherein M is less than N, the N complex fitting within transmission subspace of the dynamic range of the system.

Abstract: A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

Abstract: A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

Abstract: Parallel concatenated trellis-coding modulation is accomplished by producing coded bits (21) from uncoded bits and also producing an interleaved version (22) of the coded bits from the uncoded bits. A first coded bits-to-signal mapping (mapping 1) is applied to the coded bits to produce a first output signal (S11), and a second coded bits-to-signal mapping (mapping 2) is applied to the interleaved version of the coded bits to produce a second output signal (S22), wherein the second coded bits-to-signal mapping differs from the first coded bits-to-signal mapping.

Abstract: A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152) a digital interface (165) coupled to the digital backplane (170) to the service provider's host server (34), a conversion circuit (258) interspersed between the analog interface (152) and the digital interface (165), and a linecard microcontroller (300) configured to request bandwidth on the backplane (170) A linecard (175) incorporates a codec (250) with a code recognition mechanism (200) to monitor the Pulse Code Modulated (PCM) input from the provider. The code recognition mechanism (200) provides a way to dynamically allocate and deallocate timeslots on the backplane (170).

Abstract: A wireless communication network (10) comprising a wireless transmitter (12). The transmitter comprises a plurality of antennas (AT11, AT12), wherein each of the plurality of antennas is operable for transmitting signals. The transmitter also comprises, for each of a plurality of different user channels (Dn), circuitry (22n) for providing a plurality of groups of symbols in a first symbol group sequence (D1n). The transmitter also comprises, for each of the plurality of different user channels, circuitry (241n) for forming a first modulated symbol group sequence for the user channel by modulating the symbols in the first symbol group sequence for the user channel with a unique code that corresponds to the user channel and distinguishes the user channel from each other of the plurality of different user channels and circuitry (261) for combining the first modulated symbol group sequences and providing them for transmission by a first antenna (AT11).

Abstract: A turbo decoder in which a sliding-block MAP decoder pipelines the forward-propagating and backward-propagating computations.

Abstract: A reconfigurable co-processor adapted for multiple multiply-accumulate operations includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The co-processor includes sign extend circuits at the output of each multiplier. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair select the product, the right shifted product or pass through the inputs. The sign extend circuit for the second multiplier follows the multiplexer.

Abstract: The preferred embodiments generalize the Band Edge Component Maximization (BECM) timing recovery method and provide blind timing recovery in Quadrature Amplitude Modulation (QAM) using all the available information rather than sampling the BECM output at the symbol rate.

Abstract: A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.

Abstract: A trellis shaping method is described that may be used for suppressing DC components and/or Nyquist frequency components from the outputs of a PCM (56K) modem. The technique is based on convolutional codes. The code is generated through the use of a Viterbi decoder. Data bits are mapped for transmission into a set of n magnitudes and (n−k) sign bits s. The sign bits s are passed through (HT)−1 to get preliminary sing bits t=s (HT)−1 of size n. (HT)−1 is a matrix of size (n−k) by n which represents the left inverse of the syndrome-former matrix HT of convolutional code c=b G, defined so that G HT=0. The convolutional code is then added to sign bits t through an XOR operation to give final sign bits s (HT)−1+b G. After transmission, the final sign bits are passed through HT to give an output of (s (HT)−1+b G) (HT))=s, for recovery of the data bits.

Abstract: A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

Abstract: A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

Abstract: A method is described for reducing computational requirements during idle transmission in remote access systems incorporating digital subscriber line (DSL) modems, including asymmetrical DSL (ADSL) systems. Processing power is saved during idle transmission by generating an idle signal using low-complexity techniques. The generated idle signal is made spectrally compatible with xDSL systems, and a non-disruptive signaling scheme is used to indicate to the far-end receiver the transition between idle to active or active to idle status. A technique is presented that modulates the phase of the pilot tone to signal status transitions to the remote receiver. The computational complexity at the receiver is reduced because fill demodulation and decoding is not required to determine that an idle signal is being transmitted.

Abstract: Spectral ambiguities are resolved in transmitting data across a data communications channel from a local transmitter to a remote receiver using a quadrature amplitude modulation (QAM) scheme by augmenting the encoding-decoding process at the transmitter and receiver. At the transmitter, the encoding process is augmented by converting the mappings (Ik, Qk) into mappings (Ĩk, {tilde over (Q)}k), where Ĩk=Ik and {tilde over (Q)}k=|Qk|&agr;k and wherein &agr;k=sign({tilde over (Q)}k-1)sign(Qk). At the receiver, the decoding process is augmented by converting the mappings (k, k) into mappings (k, k), where k=k and k=|k|&bgr;k and wherein &bgr;k=sign(k)sign(k−1).

Abstract: A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing

Abstract: A discrete multitone (DMT) digital subscriber loop (xDSL) telecommunication system has a transmitter portion including a bit encoder, inverse fast Fourier transform (FFT), parallel-to-serial converter, digital-to-analog converter and line driver for transmitting data signals to a twisted pair telephone line and a receiver portion including an analog-to-digital converter, serial-to-parallel converter, forward FFT and bit decoder for receiving data signals from the twisted pair telephone line. The FFT's are implemented in 19-bit precision using a fixed point 16-bit processor. At each FFT stage, the number of sign bits in the FFT input data is examined to determine whether overflow is possible during multiply and add operations. The input data is downscaled by right shifting one or two bits if overflow is possible. If downscaling occurred, the output data is rescaled after completion of the FFT operation. If overflow is not possible, no scaling is done.