Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

Abstract: Various techniques for controlling metal-containing contamination on a semiconductor substrate are provided herein. Such techniques may involve one or more of a post-development bake treatment, a chemical treatment, a plasma treatment, a light treatment, and a backside and bevel edge clean. The techniques may be combined as desired for a particular application. In many cases, the techniques are used to address metal-containing contamination that is generated during a photoresist development operation.

Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

Abstract: Techniques described herein relate to methods, apparatus, and systems for promoting adhesion between a substrate and a metal-containing photoresist. For instance, the method may include receiving the substrate in a reaction chamber, the substrate having a first material exposed on its surface, the first material including a silicon-based material and/or a carbon-based material; generating a plasma from a plasma generation gas source that is substantially free of silicon, where the plasma includes chemical functional groups; exposing the substrate to the plasma to modify the surface of the substrate by forming bonds between the first material and chemical functional groups from the plasma; and depositing the metal-containing photoresist on the modified surface of the substrate, where the bonds between the first material and the chemical functional groups promote adhesion between the substrate and the metal-containing photoresist.

Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

Abstract: Methods, apparatus, and systems are provided herein for processing a substrate. Generally, the processing involves Spacer-on-Spacer (SoS) Self-Aligned Quadruple Patterning (SAQP) techniques. The disclosed techniques provide a novel process flow that reduces defects by ensuring that cores are not removed from the substrate until the substrate is transferred to a deposition chamber used to deposit a second spacer layer. This reduces or eliminates the risk of structural damage to features on the substrate while the substrate is being transferred or cleaned. Such structural damage is common when the cores are removed from the substrate prior to cleaning and transfer.

Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times.

Abstract: A method and apparatus for pre-conditioning a polishing pad for use in chemical mechanical planarization of semiconductor wafers is described. The apparatus includes a pre-conditioning member having a smooth surface. The method includes providing a pre-conditioning member having a smooth surface, pressing the pre-conditioning member against the polishing pad while moving the polishing pad, and flattening the surface of the polishing pad until a polishing pad flatness is achieved that may be used to achieve a desired semiconductor wafer planarity.

Abstract: A method and apparatus for conditioning a polishing pad is described, wherein the polishing pad has a polishing surface for polishing the semiconductor wafer. The method includes positioning a sonic energy generator above the polishing surface of the polishing pad, and applying sonic energy to the polishing surface of the polishing pad. The apparatus a sonic energy generator adapted to be positioned above the polishing surface, the sonic energy generator including a transducer, and a liquid carrier in flow communication with the transducer, wherein the transducer transmits sonic energy into the liquid carrier and the liquid carrier is applied to the polishing surface of the polishing belt.

Abstract: A method and apparatus for pre-conditioning a polishing pad for use in chemical mechanical planarization of semiconductor wafers is described. The apparatus includes a pre-conditioning member having a smooth surface. The method includes providing a pre-conditioning member having a smooth surface, pressing the pre-conditioning member against the polishing pad while moving the polishing pad, and flattening the surface of the polishing pad until a polishing pad flatness is achieved that may be used to achieve a desired semiconductor wafer planarity.

Abstract: A method and apparatus for conditioning a fixed-abrasive polishing pad used in chemical mechanical planarization of semiconductor wafers is described. The apparatus includes a conditioning member having a smooth surface. The method includes providing a conditioning member having a smooth surface, pressing the conditioning member against the fixed-abrasive polishing pad, and moving the fixed-abrasive polishing pad. In one embodiment, the method further comprises moving the conditioning member perpendicular to the direction of movement of the fixed-abrasive pad to compensate for variations in amounts of exposed abrasive on the fixed-abrasive pad.

Abstract: A method and apparatus for pre-conditioning a polishing pad for use in chemical mechanical planarization of semiconductor wafers is described. The apparatus includes a pre-conditioning member having a smooth surface. The method includes providing a pre-conditioning member having a smooth surface, pressing the pre-conditioning member against the polishing pad while moving the polishing pad, and flattening the surface of the polishing pad until a polishing pad flatness is achieved that may be used to achieve a desired semiconductor wafer planarity.

Abstract: A CMP polishing pad improves overall material removal rate uniformity by combining multiple polishing pad sections in a serially linked manner, where the polishing pad sections are characterized by at least two different material removal rate profiles. The polishing pad is designed by determining a wafer polishing profile for each of a group of polishing pads where each polishing pad has a unique groove configuration, determining a combination of polishing pad segments, each of the segments constructed with one of the unique groove configurations, that will combine to achieve an improved uniformity in the polishing profile, and manufacturing a polishing pad having pad sections corresponding to the analytically determined pad sections.

Abstract: A CMP polishing pad improves overall material removal rate uniformity by combining multiple polishing pad sections in a serially linked manner, where the polishing pad sections are characterized by at least two different material removal rate profiles. The polishing pad is designed by determining a wafer polishing profile for each of a group of polishing pads where each polishing pad has a unique groove configuration, determining a combination of polishing pad segments, each of the segments constructed with one of the unique groove configurations, that will combine to achieve an improved uniformity in the polishing profile, and manufacturing a polishing pad having pad sections corresponding to the analytically determined pad sections.

Abstract: A method and apparatus for pre-conditioning a polishing pad for use in chemical mechanical planarization of semiconductor wafers is described. The apparatus includes a pre-conditioning member having a smooth surface. The method includes providing a pre-conditioning member having a smooth surface, pressing the pre-conditioning member against the polishing pad while moving the polishing pad, and flattening the surface of the polishing pad until a polishing pad flatness is achieved that may be used to achieve a desired semiconductor wafer planarity.

Abstract: A method and apparatus for conditioning a polishing pad is described, wherein the polishing pad has a polishing surface for polishing the semiconductor wafer. The method includes positioning a sonic energy generator above the polishing surface of the polishing pad, and applying sonic energy to the polishing surface of the polishing pad. The apparatus a sonic energy generator adapted to be positioned above the polishing surface, the sonic energy generator including a transducer, and a liquid carrier in flow communication with the transducer, wherein the transducer transmits sonic energy into the liquid carrier and the liquid carrier is applied to the polishing surface of the polishing belt.

Abstract: A CMP polishing pad improves overall material removal rate uniformity by combining multiple polishing pad sections in a serially linked manner, where the polishing pad sections are characterized by at least two different material removal rate profiles. The polishing pad is designed by determining a wafer polishing profile for each of a group of polishing pads where each polishing pad has a unique groove configuration, determining a combination of polishing pad segments, each of the segments constructed with one of the unique groove configurations, that will combine to achieve an improved uniformity in the polishing profile, and manufacturing a polishing pad having pad sections corresponding to the analytically determined pad sections.

Abstract: A CMP polishing pad improves overall material removal rate uniformity by combining multiple polishing pad sections in a serially linked manner, where the polishing pad sections are characterized by at least two different material removal rate profiles. The polishing pad is designed by determining a wafer polishing profile for each of a group of polishing pads where each polishing pad has a unique groove configuration, determining a combination of polishing pad segments, each of the segments constructed with one of the unique groove configurations, that will combine to achieve an improved uniformity in the polishing profile, and manufacturing a polishing pad having pad sections corresponding to the analytically determined pad sections.

Abstract: A CMP polishing pad improves overall material removal rate uniformity by combining multiple polishing pad sections in a serially linked manner, where the polishing pad sections are characterized by at least two different material removal rate profiles. The polishing pad is designed by determining a wafer polishing profile for each of a group of polishing pads where each polishing pad has a unique groove configuration, determining a combination of polishing pad segments, each of the segments constructed with one of the unique groove configurations, that will combine to achieve an improved uniformity in the polishing profile, and manufacturing a polishing pad having pad sections corresponding to the analytically determined pad sections.