Abstract: A test system for functionally testing and troubleshooting microprocessor-based systems and assemblies is disclosed wherein the test system is connected in place of the microprocessor circuit of the unit being tested (UUT). The test system is itself a microprocessor-based system and includes a microprocessor circuit which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT. The test system periodically switches this microprocessor into signal communication with the UUT for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/O registers.