Patents by Inventor Albert H. Chang

Albert H. Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240313793
    Abstract: The present disclosure describes a system with an antenna, a signal generator, data converters, and an aggregator circuit. The antenna is configured to provide an input signal to the data converters. The signal generator is configured to generate a random binary sequence received by the data converters. The data converters include an analog circuit and a digital circuit configured to sample positive and negative polarities of the input signal based on the random binary sequence, reducing an offset tone in an output spectrum produced by the aggregator circuit.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Applicant: Apple Inc.
    Inventors: Albert H. CHANG, Ahmad AL MARASHLI, George P. REITSMA, Sudharsan KANAGARAJ, Hamid NEJATI, Dusan STEPANOVIC, Vahid Majidzadeh BAFAR, Mansour KERAMAT, Mahdi KHOSHGARD
  • Patent number: 7793089
    Abstract: A method comprises obtaining connectivity information from a plurality of electrical devices. Each such electrical device is separately coupled to a backplane, and at least one electrical device comprises a plurality of electrical interfaces adapted to be selectively coupled to each of multiple other electrical devices. Based on connectivity information from the at least one electrical device, the method further comprises providing configuration information to the at least one electrical device to cause the at least one electrical device to electrically couple to a target other electrical device via the backplane.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: September 7, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin B. Leigh, Michael L. Sabotta, Albert H. Chang
  • Publication number: 20080183906
    Abstract: A method comprises obtaining connectivity information from a plurality of electrical devices. Each such electrical device is separately coupled to a backplane, and at least one electrical device comprises a plurality of electrical interfaces adapted to be selectively coupled to each of multiple other electrical devices. Based on connectivity information from the at least one electrical device, the method further comprises providing configuration information to the at least one electrical device to cause the at least one electrical device to electrically couple to a target other electrical device via the backplane.
    Type: Application
    Filed: January 31, 2007
    Publication date: July 31, 2008
    Inventors: Kevin B. LEIGH, Michael L. Sabotta, Albert H. Chang
  • Patent number: 6918007
    Abstract: A single read request to a memory controller generates multiple read actions along with XOR/DATUM manipulation of that read data. Fewer memory transfers are required to accomplish a RAID5/DATUM parity update. This allows for higher system performance when memory bandwidth is the limiting system component. In implementation, a read buffer with XOR capability is tightly coupled to a memory controller. New parity does not need to be stored in the controller's memory. Instead, a memory read initiates multiple reads from memory based on an address decode. The data from the reads are multiplied and XOR'd before being returned to the requestor. In the case of a PCI-X requestor, this occurs as a split-completion.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: July 12, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Albert H. Chang, Jeff M. Carlson, Christopher Garza, Mark J. Thompson
  • Publication number: 20040049632
    Abstract: A single read request to a memory controller generates multiple read actions along with XOR/DATUM manipulation of that read data. Fewer memory transfers are required to accomplish a RAID5/DATUM parity update. This allows for higher system performance when memory bandwidth is the limiting system component. In implementation, a read buffer with XOR capability is tightly coupled to a memory controller. New parity does not need to be stored in the controller's memory. Instead, a memory read initiates multiple reads from memory based on an address decode. The data from the reads are multiplied and XOR'd before being returned to the requestor. In the case of a PCI-X requestor, this occurs as a split-completion.
    Type: Application
    Filed: September 9, 2002
    Publication date: March 11, 2004
    Inventors: Albert H. Chang, Jeff M. Carlson, Christopher Garza, Mark J. Thompson
  • Publication number: 20030126242
    Abstract: A method and system for network booting of clients linked to a network. The method includes receiving a boot request from a networked client device and determining a target. The target is determined for the client device and a boot volume is selected from a set of client image copies. Each client image copy is unique to a client device and is created using a snapshot of a base boot image with a virtual copy or reverse snapshot of the base image being stored for each client device. The method continues with logging the client into the target and providing direct access to the allocated client image copy. The client device remotely boots from the client boot volume(s) or blocks on a remote storage device. Each client image copy includes the base boot image and information specific to the client. The client information is updated with writes to automatically allocated client-specific blocks.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 3, 2003
    Inventor: Albert H. Chang
  • Patent number: 6370616
    Abstract: A memory interface controller employs a DATUM multiplier within a destination address to perform DATUM RAID operations. If destination data is in an XOR memory address space, then the multiplier can indicate to multiply source data by the multiplier and XOR that resulting data with the destination data. The DATUM multiplier can be read in response to detection of a memory command. The multiplier alternatively can be used in connection with an input/output bus write command to write source data from the input/output address space to an XOR memory address space. In response to such a write command, the input/output bus data in the input/output address space is multiplied by the multiplier; that resulting data is XORed with the destination data in the XOR memory address space. The multiplier in this case can be within an input/output bus address associated within the input/output bus data.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: April 9, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Ryan A. Callison, Christopher Garza, Albert H. Chang, Hubert Brinkman
  • Patent number: 6370611
    Abstract: A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: April 9, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Ryan A. Callison, William C. Galloway, Christopher Garza, Albert H. Chang