Patents by Inventor Albert L. Chan

Albert L. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5883946
    Abstract: A system for interfacing a service activation controller and a service management system allows a remote system to generate, update and delete call processing records and to create, update and delete tables. A provisioning message with one or more requests is sent to the service management system to process each request in the message, which identifies a unique logic template and one or more data templates and includes customized call variables data for inserting into a service record created from the template or updating an already created record. The resulting service record is activated by inputting the request to an integrated service point.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: March 16, 1999
    Assignee: Bell Communications Research, Inc.
    Inventors: Douglas Beck, Albert L. Chan, Sary Tauv, Lei Lei Wang, Patrick K. White
  • Patent number: 5835405
    Abstract: A structure and a method provide a programmable logic device including a number of generic logic blocks and one or more application-specific block. Such application-specific block implements a specific function, such as a register file or a memory array. In one embodiment, the application specific block is programmable to be either one or more single-port memory array, a first-in-first-out (FIFO) memory, or a dual port memory array. In another embodiment, the application-specific block can be configured to be a register file, a number of counters, a number of timers, or a shift register. The application-specific block can be used in conjunction with programmable logic arrays for multiplexing input and output signals into and out of the application-specific block. Interconnectivity between the generic logic blocks and the application-specific blocks using a global routing resource integrates into a programmable logic device functions otherwise difficult to implement using only generic logic blocks.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: November 10, 1998
    Assignee: Lattice Semiconductor Corporation
    Inventors: Cyrus Y. Tsui, Kapil Shankar, Albert L. Chan
  • Patent number: 5506517
    Abstract: An output enable structure and a method for providing output capability to an input/output cell of a programmable logic device are shown. In one embodiment, one of two global output enable signals, a test output enable signal, and two product term output enable signals is selected for controlling an output buffer of an I/O cell. Additional pin-out flexibility is provided by routing the input signal received at an I/O pin to neighboring I/O cells.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: April 9, 1996
    Assignee: Lattice Semiconductor Corporation
    Inventors: Cyrus Y. Tsui, Albert L. Chan, Ming C. Hsu
  • Patent number: 5412260
    Abstract: A structure and a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions. The SDI, SCLK, MODE and SDO connections required for in-system programming and the TDI, TCK, TMS and TDO connections required for boundary-scan testing are multiplexed such that they are provided from the same four pins. An in-system programming enable pin is used to control the multiplexing of these pins. In an alternative embodiment, both in-system programming and boundary-scan testing are performed using the same pins and the same state machine. The test logic architecture specified in IEEE Standard 1149.1-1990 is utilized. To implement the in-system programming instructions, the instruction register of Std. 1149.1-1990 is modified to include private instructions which perform the desired programming functions.
    Type: Grant
    Filed: August 13, 1993
    Date of Patent: May 2, 1995
    Assignee: Lattice Semiconductor Corporation
    Inventors: Cyrus Y. Tsui, Albert L. Chan, Kapil Shankar, Ju Shen
  • Patent number: 5191243
    Abstract: An output logic macrocell ("OLMC") containing an exclusive OR gate is associated with the product terms and other outputs of a logic block such as a programmable logic array. The OLMC is capable of providing enhanced functions, including cascaded exclusive OR gates, function sharing, T and J-K flip-flop emulation, asynchronous clocking, and a reset selection. In addition, a logic block is used as the source of an asynchronous clock pulse and is connected to the global clock distribution system of a device such as a high density programmable logic device.
    Type: Grant
    Filed: May 6, 1991
    Date of Patent: March 2, 1993
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ju Shen, Albert L. Chan, Kapil Shankar, Cyrus Tsui
  • Patent number: 5162679
    Abstract: A sense amplifier circuit is disclosed which utilizes a field effect transistor having a negative threshold voltage to provide a faster switching speed for a given current consumption. A depletion mode transistor is utilized as the feedback transistor, with the gate of the depletion mode transistor being coupled to the output of the second stage of the sense amplifier. The first stage of the sense amplifier includes in addition to the depletion mode transistor a second field effect transistor connected in series with said feedback transistor, with the gate and drain of the second transistor being commonly connected. The sense amplifier circuit also includes third and fourth stages providing inversion and amplification of the signal provided at the output of the second stage, with the third and fourth stages comprising a depletion load inverter and a CMOS inverter, respectively.
    Type: Grant
    Filed: May 3, 1991
    Date of Patent: November 10, 1992
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ju Shen, Albert L. Chan, Chan-Chi J. Cheng
  • Patent number: 5138198
    Abstract: A programmable logic device is disclosed which includes sense amplifiers for determining the programmed/unprogrammed state of product terms coupled to respective ones of the sense amplifiers. A control circuit is provided for the sense amplifiers to permit, under control from a control signal, disabling sense amplifiers which are not being used in the achievement of the logical function of the programmable logic device to avoid unnecessary use of current by the sense amplifiers which are not operative for the function being implemented. In addition to eliminating current drain by the unused sense amplifier, the control circuit also ensures that a low output signal will always be provided at the output of the disabled sense amplifier to avoid potentially indicating an incorrect logical output from the sense amplifier which is connected to other devices in the programmable logic device.
    Type: Grant
    Filed: May 3, 1991
    Date of Patent: August 11, 1992
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ju Shen, Albert L. Chan, Chan-Chi J. Cheng
  • Patent number: 5130574
    Abstract: A programmable logic device is disclosed which includes a programmable AND array, a plurality of logic circuits connected to groups of product term outputs from the AND array for performing a logical OR operation of the product term inputs and the programmable logic device includes programmable OR circuitry for selectively connecting one or more of the ORed groups of product terms to one or more outputs of the programmable logic device. The programmable OR circuit permits product term steering and sharing.
    Type: Grant
    Filed: May 6, 1991
    Date of Patent: July 14, 1992
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ju Shen, Albert L. Chan, Kapil Shankar, Cyrus Tsui
  • Patent number: 4625311
    Abstract: A field programmable array logic circuit is described wherein existing sensing circuitry is employed along with circuitry to enable every fuse location to be isolated, so that both a.c. and verification testing takes place under the same conditions, i.e. voltage levels and frequency, which occurs during normal operation of the programmed circuit.
    Type: Grant
    Filed: June 18, 1984
    Date of Patent: November 25, 1986
    Assignee: Monolithic Memories, Inc.
    Inventors: Mark E. Fitzpatrick, Cyrus Y. Tsui, Andrew K. Chan, Albert L. Chan