Abstract: A device comprising i) input ports and output ports for receiving and transmitting data packets, ii) a receiver to extract primary switching or routing data and secondary data to be handled and to associate the secondary data with a selected storage address, iii) a memory for storing the secondary data extracted at the storage address, iv) a switching stage and a routing stage configured to receive the storage address and the primary switching or routing data and to determine tertiary data designating at least one of the output ports and to determine new primary data, v) extracting the tertiary data and the new primary data from the switching stage and the routing stage to deliver the data and the storage address as a function of a selected criterion, and vi) sending the secondary data stored at the storage address, combined with the new primary data to each output port designated by the tertiary data.

Abstract: A data packet switching node, for use in an asynchronous digital network, that has an input stage that cuts data packets into segments of constant length, a switching matrix having input ports and output ports supporting identical bit rates B switching the segments and an output stage reconstructing the data packets from the segments supplied by the output ports of said switching matrix. The input stage has at least one input interface with a bit rate equal to a multiple of B, ki*B, and splits the data packet into ki input ports of the switching matrix. The output stage has at least one output interface with a bit rate equal to a multiple of B, ko*B, and reconstructs a data packet with a bit rate equal to ko*B by concatenating segments supplied by ko output ports of the switching matrix where ki*ko>1.

Abstract: A handling device comprises i) input ports (4) and output ports (7) for receiving and transmitting data packets, ii) receiver means (3) adapted to extract primary switching or routing data and secondary data to be handled and to associate said data with a selected storage address (FSA(n)), iii) a memory (5) for storing the secondary data extracted at the storage address, iv) switching a stage (8) and a routing stage (9) adapted to receive the storage address and the primary switching or routing data and to determine tertiary data designating at least one of said output ports (7) and new primary routing data from said data and data stored in a switching table or a routing table, v) monitoring means (10) adapted to extract the tertiary data and the new primary data from the switching stage (8) and the routing stage (9) and to deliver said data and the storage address (FSA(n)) as a function of a selected criterion, and vi) sending means adapted to extract from said memory (5) the secondary data stored at the sto

Abstract: A data routing device comprises, firstly, a management module (9) having a buffer memory (10) divided into m sub-memories storing primary routing data and a storage address (FSA(n))at selected addresses in the form of data packet segment portions, which sub-memories are associated with secondary data to be routed and adapted to deliver some of the portions that they store on command at m first parallel outputs, and, secondly, a transfer module (12) adapted i) to receive selected storage addresses of segment portions from the management module (9), ii) to deliver said storage addresses to the management module as a function of a selected criterion so as to receive in return at the first parallel outputs the segment portions stored at said storage addresses, and iii) to direct the portions belonging to different segments to at least two routing tables so as to determine in parallel, portion by portion, from data stored in said routing tables and from an analysis of the various segments, tertiary data to designa

Abstract: The invention relates to a data packet switching node to be used in an asynchronous digital network.

Abstract: In a packet switching (packet-based) network, such as a frame relay (FR) network, which includes network resources made up of networked elements and customer premises equipment interconnected by one or more physical paths, a Virtual Private Network (VPN) is built above the underlying packet-based network and includes selected portions of the packet-based network resources. The VPN is a collection of logical nodes and virtual paths (VPs) and includes one or more virtual circuits (VCs), each VC being a logical connection between VC terminators including network elements and customer premises equipment. Segments of the VCs are carried by VPs, each VP being a logical connection established between two VP terminators which are located in either network elements or customer premises equipment. One or more VPs are multiplexed on a physical path (PP). Each VP is allocated a positive guaranteed bandwidth (VP-CIR), and each VC on a VP is also allocated a bandwidth (VC-CIR) greater than or equal to zero.

Abstract: In a packet-based communications network (100), a virtual connection is established between a source node (102a) and a destination node (102b), which may traverse one or more intermediate nodes (105). During the flow of packets along the virtual connection in a forward direction, from the source node (102a) to the destination node (102b), each node measures the utilization of critical resources (CUF), and this utilization information is inserted into return packets flowing in the backward (return) direction, from the destination node (102b) to the source node (102b). CUF is indicative of the maximum utilization of any resource in the virtual connection forward path. If the network utilization information indicates that the resources of a virtual connection are under-utilized, the submission rate (SIR) of packets onto the virtual connection is increased.

Abstract: A frame switching relay switches frames between input and output paths by multiplexing of the paths at frame cell level. A frame is divided into cells having a constant number of bits, whereas the frames are of variable length. The switching relay only retransmits frames that have been completely written in the buffer memory. A context memory preserves the address of the first cell at the start of the writing of a frame in the buffer memory, and memorizes the address of the output path for which the frame is destined, until the frame is completely written. A checking circuit checks that the writing of the frame does not cause an "overflow" in the buffer memory, by updating the number of cells awaiting reading and respectively associated with the output paths. If there is no overflow, the address of the first cell of the frame is written in one of the address queues as a function of the destination output path address.

Abstract: A communication system is designed to equip an asynchronous time-division network and to enable terminals linked to the network to communicate in the no-connection mode. The system comprises a ring management device and components distributed among the terminals and interfacing the terminals with a virtual ring for managing the production, reception and transmission of data cells. The ring management device is linked via the network to each of the terminals in order to control the connection/disconnection requests coming from the terminals and to supply information concerning cell routing to the terminals linked to the ring. A terminal has a particular role as a pilot for regulating the rate of the data cells in the virtual ring. Another purpose of the pilot terminal is to eliminate the altered cells. Furthermore, there is provided in each of the terminals a device for limiting its rate to a maximum value.

Abstract: A first switching network embodying the invention is a subscriber installation having a chain structure. In the network, the switching is distributed over a plurality of switches each connecting a terminal to the network. A second embodiment is a business network having a star-chain structure and comprising a plurality of sub-networks of chain type. The sub-networks are star connected to central switches which operate in a load sharing mode. According to the method embodying the invention, the terminals connected to the network assume themselves the responsibility for determining communication routes through the network. During a communication set-up phase, caller and callee terminals transmit call packets which are disseminated to all terminals in order to measure two so-called "distances" respectively between the caller and the callee and between the callee and the caller. These distances are after included in data packets for routing said packets.

Abstract: The circuit embodying the invention comprises a pointer memory memorizing J=16 decremented write pointers associated with J=16 buffer queues. A channelling word supplied conjointly to incoming data and indicating the buffer queue in which this data is to be written, addresses the corresponding decremented write pointer. The write pointer and the channelling word form a write address for a buffer memory used as a medium for the J=16 queues. A comparator detects equality between the write pointer and the read pointer and in this case inhibits the acceptance of the incoming data which would overlay data not yet read. Logic means associated with the comparator control the updating, by possible incrementation, of the write pointer values contained in the pointer memory, after each data read in the buffer queues. This circuit is particularly well suited for use in an asynchronous self-channelling packet time-division switching system.

Abstract: The packet flow of each virtual circuit is measured and compared to an allocated average value. At each transmission authorization request (DAE'), when found to be less than the average value, a positive difference brings about an authorization to transmit and is translated into a right to transmit which is proportional to the time span since the previous request, the right to transmit being accumulated. When it is found to be greater than the average value, a negative difference brings about, if the number of accumulated transmission rights is positive, on one hand, the authorization to transmit and, on the other hand, a decrementing of the accumulated number, and if the accumulated number is nil, a refusal of authorization to transmit.Some examples of systems carrying out the process are described.The process and systems are applicable in particular to packets carried by asynchronous time multiplexers.

Abstract: The apparatus is designed to use a single transmission medium to multiplex frames consisting of any number of bits of different origins which have previously passed through an asynchronous time-division network and are delivered in the form of packets of fixed length interlaced by an asynchronous time-division multiplex. A detection and write management circuit receives the packets and writes them in a packet memory as and when they arrive. In parallel with the writing of the packets, the addresses of the memory cell having memorized the packets of a given frame are written in the form of a string of frame addresses in a second memory. After complete writing of a frame in the first memory, a frame read and transmission circuit completely reads the frame using the corresponding address string and transmits it in serial form on the transmission medium. Packing words such as flags are inserted between the frames read.

Abstract: A system for switching information packets assigned with two levels of semantic priority between entering time multiplex lines and outgoing time multiplex lines, a storage address of a packet in a buffer memory of the system being stored in a queueing file associated with each outgoing time multiplex line designated to transmit the packet, comprising a field point (state) memory whose words each are comprised of as many bits as there are outgoing time multiplex lines, the addresses of the the field point memory corresponding to those of the buffer memory, each bit of the words being at "1" when the packets stored at the same address as the words and designated for an outgoing time multiplex line corresponds to a high level semantic priority bit and has not yet been transmitted by the outgoing multiplex line concerned, each packet storage address being chosen from the addresses of the field point memory addressing all bits of which are at "0".