Abstract: An adaptive analog parallel combiner circuit for receiver data recovery from a communication signal is provided. The circuit includes a summer that sums outputs of a plurality of filter taps in parallel, including zeroth and first through Nth filter taps, each filter tap having as input the communication signal or a version thereof, wherein N is a finite integer greater than or equal to two. The zeroth filter tap has an amplifier with gain controlled by a zeroth adaptive gain control coefficient, and each of the first through Nth filter taps having an all pass filter and gain controlled amplification, with gain controlled by a corresponding one of a first through Nth adaptive gain control coefficients and the all pass filter implementing a transfer function having a zero and a pole equaling each other and at a base frequency divided by a corresponding integer from one through N.

Abstract: Systems, methods, circuits and computer-readable mediums for regulators, e.g., low-dropout (LDO) regulators, with load-insensitive compensations are provided. An example regulator includes an amplifier operable to receive an input voltage and a feedback voltage, a follower responsive to an output voltage of the amplifier and operable to supply a regulated voltage to a load coupled to the follower, and a feedback circuit coupled to the load and the amplifier and operable to provide the feedback voltage. The amplifier is operable to have a substantially unity gain beyond a resonant frequency of the amplifier.

Abstract: An adaptive analog parallel combiner circuit for receiver data recovery from a communication signal is provided. The circuit includes a summer that sums outputs of a plurality of filter taps in parallel, including zeroth and first through Nth filter taps, each filter tap having as input the communication signal or a version thereof, wherein N is a finite integer greater than or equal to two. The zeroth filter tap has an amplifier with gain controlled by a zeroth adaptive gain control coefficient, and each of the first through Nth filter taps having an all pass filter and gain controlled amplification, with gain controlled by a corresponding one of a first through Nth adaptive gain control coefficients and the all pass filter implementing a transfer function having a zero and a pole equaling each other and at a base frequency divided by a corresponding integer from one through N.

Abstract: A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level.

Abstract: Systems, methods, circuits and computer-readable mediums for regulators, e.g., low-dropout (LDO) regulators, with load-insensitive compensations are provided. An example regulator includes an amplifier operable to receive an input voltage and a feedback voltage, a follower responsive to an output voltage of the amplifier and operable to supply a regulated voltage to a load coupled to the follower, and a feedback circuit coupled to the load and the amplifier and operable to provide the feedback voltage. The amplifier is operable to have a substantially unity gain beyond a resonant frequency of the amplifier.

Abstract: An adaptive analog parallel combiner circuit for receiver data recovery from a communication signal is provided. The circuit includes a summer that sums outputs of a plurality of filter taps in parallel, including zeroth and first through Nth filter taps, each filter tap having as input the communication signal or a version thereof, wherein N is a finite integer greater than or equal to two. The zeroth filter tap has an amplifier with gain controlled by a zeroth adaptive gain control coefficient, and each of the first through Nth filter taps having an all pass filter and gain controlled amplification, with gain controlled by a corresponding one of a first through Nth adaptive gain control coefficients and the all pass filter implementing a transfer function having a zero and a pole equaling each other and at a base frequency divided by a corresponding integer from one through N.

Abstract: A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level.

Abstract: A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level.

Abstract: Apparatus and methods are described for space-efficient, high-speed data communications for integrated circuits. Bandwidth is multiplied by using multiple individual wireline communications channels coupled to form a communications lane. The data receiver for a channel implements symbol-rate equalization and crosstalk filtering that is space efficient, allowing high-speed data communications to be added as an ancillary function to an IC.

Abstract: According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.

Abstract: According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.

Abstract: Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.

Abstract: According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.

Abstract: An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a large number of communications channels.

Abstract: Incoming data at a high-speed serial receiver is digitized and then digital signal processing (DSP) techniques may be used to perform digital equalization. Such digital techniques may be used to correct various data anomalies. In particular, in a multi-channel system, where crosstalk may be of concern, knowledge of the characteristics of the other channels, or even the data on those channels, may allow crosstalk to be subtracted out. Knowledge of data channel geometries, particularly in the context of backplane transmissions, may allow echoes and reflections caused by connectors to be subtracted out. As data rates increase, fractional rate processing can be employed. For example, the analog-to-digital conversion can be performed at half-rate and then two DSPs can be used in parallel to maintain throughput at the higher initial clock rate. At even higher rates, quadrature techniques can allow analog-to-digital conversion at quarter-rate, with four DSPs used in parallel.

Abstract: An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a large number of communications channels.

Abstract: A hybrid circuit is disclosed for effectively communicating information over a telecommunications line to which a transmitter and receiver are connected. The hybrid circuit is configured as a filter for filtering at the receiver input signals at predetermined frequencies appearing on the transmitter output and the telecommunications line. The filter circuit additionally forms a capacitive divider for scaling signals appearing at the transmitter output and canceling the scaled signals at the receiver input with related signals appearing on the telecommunications line. In one embodiment of the present invention for communicating using the ADSL protocol, the filter circuit is a first order high pass filter.

Abstract: An echo cancellation functionality taps a digital transmit signal from a transmit channel for processing through an adaptive filter of an echo channel to generate an echo cancellation signal. The adaptive filter has a transfer function substantially matching an echo transfer function which defines a relationship between the transmit signal and an unwanted echo component corrupting an analog receive signal. The echo cancellation signal is digital-to-analog converted to an analog signal and then subtracted from the analog receive signal to substantially cancel out the unwanted echo component. The echo cancellation functionality may be configured in a training mode to generate an error signal used to adaptively configure the adaptive filter transfer function to substantially match the echo transfer function. When in training mode, certain components of an adaptation loop which contribute to a feedback loop transfer function are selectively by-passed.