Abstract: A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.

Abstract: A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.

Abstract: An oscillator is provided that includes at least one capacitor, at least one comparator, and at least one device for charging or discharging the at least one capacitor. The capacitor is coupled to the comparator. The comparator compares the voltage on the capacitor with a reference voltage, and activates the device so as to command the charging or the discharging of the capacitor. The oscillator also comprises a circuit for supplying a preset voltage to the comparator when the device commands the charging of the capacitor, so that the comparator compares the reference voltage diminished by the preset voltage with the voltage on the capacitor, or the voltage on the capacitor added to the preset voltage with the reference voltage.

Abstract: A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.