Abstract: The present invention relates to a memory cell comprising: a resistive structure; at least two electrodes coupled to the resistive structure, and at least one hydrogen reservoir structure, wherein the application of an electrical signal to one of the at least two electrodes causes the electrical resistance of the resistive structure to be modified by altering a hydrogen-ion concentration in the resistive structure.

Abstract: A metal chalcogenide material is deposited into holes within a substrate surface. The method comprises obtaining a hydrophilic substrate surface; obtaining a solution of a hydrazine-based precursor of a metal chalcogenide; applying the solution onto the substrate to fill the holes with said precursor; and thereafter annealing the precursor to convert said precursor to said metal chalcogenide thereby producing holes in the substrate surface filled with a metal chalcogenide material.

Abstract: A memory cell and a method of making the same. An insulating material is deposited on a substrate. A via is produced in the substrate and a conductive lower block is disposed within the via. A step spacer comprised of insulating material is disposed in the via above the conductive lower block. Phase change material is disposed above the conductive lower block and bound within the step spacer. A conductive upper block comprised of conductive material is formed over the phase change material.

Abstract: Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.

Abstract: A method of assembling arrays of small particles or molecules using an atomic force microscope to define ferroelectric domains includes depositing a ferroelectric thin film upon a substrate forming workpiece, then using an atomic force microscope having a conductive, tip for generating a pattern on this thin film to define desired nano-circuit patterns. Next, exposure of this thin film to a solution containing chemical species which selectively adsorb or accumulate under the influence of electrophoretic forces in selected regions of this thin film.

Abstract: A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.

Abstract: A method for changing the surface termination of a perovskite substrate surface, an example of which is the conversion of B-site terminations of a single-crystal STO substrate to A-site terminations. The method generally comprises the steps of etching the substrate surface by applying a reactive plasma thereto in the presence of fluorine or another halogen, and then annealing the substrate at a temperature sufficient to regenerate a long range order of the surface, i.e., the surface termination contributes to a better long range order in a film epitaxially grown on the surface. More particularly, the resulting substrate surfaces predominantly contains A-site surface terminations, i.e., SrO for STO (100) substrates. As a result, disadvantages associated with B-site terminated perovskite substrate surfaces are avoided. A suitable etching treatment is a low power oxygen ashing in the presence of low halogen levels.

Abstract: A method of manufacturing an integrated circuit device includes forming a laminated structure having a first side and a second side, the first side includes a first type Mott channel layer and the second side includes a second type Mott channel layer. A first source region and a first drain region is formed on the first side, a second source region and a second drain region is formed on the second side, a first gate region is formed on the second side, opposite the first source region and the first drain region and a second gate region is formed on the first side, opposite the second source region and the second drain region. The first source, the first drain and the first gate comprise a first type field effect transistor and the second source, the second drain and the second gate comprise a second type field effect transistor.

Abstract: A method of assembling arrays of small particles or molecules using an atomic force microscope to define ferroelectric domains includes depositing a ferroelectric thin film upon a substrate forming workpiece, then using an atomic force microscope having a conductive, tip for generating a pattern on this thin film to define desired nano-circuit patterns. Next, exposure of this thin film to a solution containing chemical species which selectively adsorb or accumulate under the influence of electrophoretic forces in selected regions of this thin film.

Abstract: A method for constructing oxide electrodes for use in an OxFET device is disclosed. The electrodes are formed by first depositing a double layer of conducting perovskite oxides onto an insulating oxide substrate. A resist pattern with the electrode configuration is then defined over the double layer by means of conventional lithography. The top oxide layer is ion milled to a depth preferably beyond the conducting oxide interface, but without reaching the substrate. Chemical etching or RIE is used to remove the part of the lower conductive oxide layer exposed by ion milling without damaging the substrate. Source and drain electrodes are thereby defined, which can be then be used as buried contacts for other perovskites that tend to react with metals. Also disclosed is a field effect transistor structure which includes these source and drain electrodes in a buried channel configuration.

Abstract: A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.

Abstract: A method of manufacturing an integrated circuit device includes forming a laminated structure having a first side and a second side, the first side includes a first type Mott channel layer and the second side includes a second type Mott channel layer. A first source region and a first drain region is formed on the first side, a second source region and a second drain region is formed on the second side, a first gate region is formed on the second side, opposite the first source region and the first drain region and a second gate region is formed on the first side, opposite the second source region and the second drain region. The first source, the first drain and the first gate comprise a first type field effect transistor and the second source, the second drain and the second gate comprise a second type field effect transistor.

Abstract: A method for changing the surface termination of a perovskite substrate surface, an example of which is the conversion of B-site terminations of a single-crystal STO substrate to A-site terminations. The method generally comprises the steps of etching the substrate surface by applying a reactive plasma thereto in the presence of fluorine or another halogen, and then annealing the substrate at a temperature sufficient to regenerate a long range order of the surface, i.e., the surface termination contributes to a better long range order in a film epitaxially grown on the surface. More particularly, the resulting substrate surfaces predominantly contains A-site surface terminations, i.e., SrO for STO (100) substrates. As a result, disadvantages associated with B-site terminated perovskite substrate surfaces are avoided. A suitable etching treatment is a low power oxygen ashing in the presence of low halogen levels.

Abstract: A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.

Abstract: A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.

Abstract: A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.

Abstract: A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.

Abstract: A combination of a radio frequency identification transponder (RFID Tag) and to a magnetic electronic article surveillance (EAS) device is disclosed.

Abstract: A tag structure suitable for attachment to an object and for being remotely sensed, includes at least one soft magnetic element mounted for being excited in an inhomogeneous magnetic field. The soft magnetic element includes first and second ends and is clamped at at least one of the first and second ends. Each soft magnetic element responds to the excitation to produce a unique, time-varying magnetic field corresponding to its resonant frequency, when excited. A system incorporating the tag includes an excitation device and a detector for detecting the mechanical vibrations of the soft magnetic element.

Abstract: A radio frequency (RF) multibit tag structure useful for identifying objects of interest is described. An array of thin cantilevers of slightly different lengths produced by differential etching are coated with a soft magnetic material which upon interrogation with an RF magnetic field vibrate at their resonant frequencies in the presence of an appropriate bias or direct current (DC) field. The oscillating magnetic fields generated by the vibrating bars and the stationary DC field can be readily detected by a receiver and processed to determine the code of the tag and thus provide information related to the object.