Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Abstract: Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to positioning signal and ground vias, or ground planes, in a glass core to control impedance within a package. Laser-assisted etching processes may be used to create vertical controlled impedance lines to enhance bandwidth and bandwidth density of high-speed signals on a package. Other embodiments may be described and/or claimed.

Abstract: Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Abstract: Embodiments disclosed herein include package substrates with angled vias and/or via planes. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a first pad is on the first surface, and a second pad on the second surface, where the second pad is outside a footprint of the first pad. In an embodiment, the package substrate further comprises a via through a thickness of the core, where the via connects the first pad to the second pad.

Abstract: A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

Abstract: Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

Abstract: Embodiments disclosed herein include multi-die modules and methods of assembling multi-die modules. In an embodiment, a multi-die module comprises a first die. In an embodiment the first die comprises a first pedestal, a plateau around the first pedestal, and a stub extending up from the plateau. In an embodiment, the multi-die module further comprises a second die. In an embodiment, the second die comprises a second pedestal, where the second pedestal is attached to the first pedestal.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.

Abstract: Embodiments disclosed herein include package substrates with antennas on the core. In an embodiment, a package substrate comprises a core with a first surface and a second surface. In an embodiment, a first conductive plane is formed into the core, where the first conductive plane is substantially orthogonal to the first surface, and a second conductive plane is formed into the core, where the second conductive plane is substantially orthogonal to the first surface. In an embodiment, an antenna is on the core, where the antenna is between the first conductive plane and the second conductive plane.

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a glass core, and a vertically oriented inductor embedded in the glass core. In an embodiment, the inductor comprises vertical vias through the glass core, and where the vertical vias are electrically coupled together by conductive traces over a surface of the glass core to provide a plurality of conductive turns.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to creating capacitors at the interface of a glass substrate. These capacitors may be three-dimensional (3-D) capacitors formed using trenches within the glass core of the substrate using laser-assisted etching techniques. A first electrode may be formed on the glass, including on the surface of trenches or other features etched in the glass, followed by a deposition of a dielectric material or a capacitive material. A second electrode may then be formed on top of the dielectric material. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include package substrates with filter architectures. In an embodiment, a package substrate comprises a core with a first surface and a second surface, and a filter embedded in the core. In an embodiment, the filter comprises a ground plane, where the ground plane is substantially orthogonal to the first surface of the core, and a resonator adjacent to the ground plane.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass interposers or substrates that may be created using a glass etching process to enable highly integrated modules. Planar structures, which may be vertical planar structures, created within the glass interposer may be used to provide shielding for conductive vias in the glass interposer, to increase the signal density within the glass substrate and to reduce cross talk. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein comprise package substrates and methods of forming such package substrates. In an embodiment, a package substrate comprises a core, where the core comprises glass. In an embodiment, an opening if formed through the core. In an embodiment, a magnetic region is disposed in the opening.

Abstract: Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related creating millimeter wave components within a glass core of a substrate within a semiconductor package. These millimeter wave components, which include resonators, isolators, directional couplers, and circulators, may be combined to form other structures such as filters or multiplexers. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include package substrates and methods of fabricating such substrates. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. The package substrate further comprises a via hole through the core. In an embodiment the via hole comprises a first portion, a second portion, and a perforated ledge between the first portion and the second portion. In an embodiment, the package substrate further comprises a via filling the via hole.

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.

Abstract: Embodiments disclosed herein include a package substrate and methods of fabricating such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface, and a via through the core. In an embodiment a first pad is over the via, and the first pad is embedded within the core with a third surface that is substantially coplanar with the first surface of the core. In an embodiment, a second pad is over the via, where the second pad is embedded within the core with a fourth surface that is substantially coplanar with the second surface of the core.