Patents by Inventor Alessandro Minzoni

Alessandro Minzoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411497
    Abstract: A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.
    Type: Application
    Filed: September 13, 2020
    Publication date: December 31, 2020
    Inventors: Wenliang Chen, Lin Ma, Alessandro Minzoni
  • Publication number: 20200364547
    Abstract: The present disclosure relates to a neural network artificial intelligence chip and a method for forming the same. The neural network artificial intelligence chip includes: a storage circuit, that includes a plurality of storage blocks; and a calculation circuit, that includes a plurality of logic units, the logic units being correspondingly coupled one-to-one to the storage blocks, and the logic unit being configured to acquire data in the corresponding storage block and store data to the corresponding storage block.
    Type: Application
    Filed: April 17, 2020
    Publication date: November 19, 2020
    Applicants: ICLEAGUE Technology Co., Ltd., AP Memory Technology Corp.
    Inventors: Wenliang CHEN, Eugene Jinglun TAM, Lin MA, Joseph Zhifeng XIE, Alessandro MINZONI
  • Patent number: 10811402
    Abstract: The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 20, 2020
    Assignee: AP Memory Technology Corp.
    Inventors: Wenliang Chen, Lin Ma, Alessandro Minzoni
  • Patent number: 10769012
    Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, a flag bit array, an ECC encoding module, an ECC decoding module, a flag bit generation module and a flag bit detection module; wherein: the flag bit generation module is configured, when data is being written, to generate a flag bit and an encode enable signal, the flag bit being stored in the flag bit array, and the encode enable signal being used to control the operation of the ECC encoding module; the ECC encoding module is configured to encode the data to be written according to the ECC algorithm preset therein so as to generate parity bits; the ECC array is configured to store the generated parity bits; the flag bit detection module is configured, when data is being read, to detect the flag bit and control the operation of the ECC decoding module; and the ECC decoding module is configured to detect and correct erroneous data using the parity bits from the ECC array and the data from the data
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 8, 2020
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventor: Alessandro Minzoni
  • Publication number: 20200212027
    Abstract: The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Inventors: WENLIANG CHEN, LIN MA, ALESSANDRO MINZONI
  • Patent number: 10665317
    Abstract: A method of ECC encoding a DRAM and a DRAM thereof. The method comprises determining whether to encode the data according to the value of a flag bit while the DRAM is being refreshed. The ECC encoding module encodes data only if of the flag bit setting and detecting module generates an enable signal. As a result, the length of the valid data for ECC encoding can be guaranteed to comply with the requirements of ECC encoding.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 26, 2020
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventor: Alessandro Minzoni
  • Publication number: 20180336091
    Abstract: The present invention relates to a method of correcting an error in a memory array in a DRAM during a read operation, wherein the memory array includes a data array and an ECC array, the method comprising: reading data from the memory array; when the data contains one or more erroneous data bits, correcting the erroneous data bits by an ECC decoding and correcting module in the DRAM; registering only corrected erroneous data bits and their positions in a register; controlling a plurality of write drivers in the DRAM by the register so as to write only the corrected erroneous data bits back to the memory array. The invention also relates to a DRAM.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 22, 2018
    Inventor: Alessandro Minzoni
  • Publication number: 20180336090
    Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, a flag bit array, an ECC encoding module, an ECC decoding module, a flag bit generation module and a flag bit detection module; wherein: the flag bit generation module is configured, when data is being written, to generate a flag bit and an encode enable signal, the flag bit being stored in the flag bit array, and the encode enable signal being used to control the operation of the ECC encoding module; the ECC encoding module is configured to encode the data to be written according to the ECC algorithm preset therein so as to generate parity bits; the ECC array is configured to store the generated parity bits; the flag bit detection module is configured, when data is being read, to detect the flag bit and control the operation of the ECC decoding module; and the ECC decoding module is configured to detect and correct erroneous data using the parity bits from the ECC array and the data from the data
    Type: Application
    Filed: May 17, 2018
    Publication date: November 22, 2018
    Inventor: Alessandro Minzoni
  • Publication number: 20180336959
    Abstract: The present invention relates to a method of ECC encoding a DRAM and a DRAM. The method comprises determining whether to encode the data according to the value of a flag bit while the DRAM is being refreshed. The ECC encoding module encodes data only of the flag bit setting and detecting module generates an enable signal. The advantage of the method is that the length of the valid data for ECC encoding can be guaranteed to comply with the requirements of ECC encoding.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 22, 2018
    Inventor: Alessandro Minzoni
  • Patent number: 9652323
    Abstract: A computer memory access method includes: receiving external data with a prefetching length, the external data having an unmasked first data portion and a masked second data portion; writing the unmasked first data portion to a corresponding data storage unit of a computer memory by a writing unit and reading a third data portion corresponding to the masked second data portion from the data storage unit by a reading unit; producing modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion; generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and then writing the parity bits to a parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 16, 2017
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventors: Alessandro Minzoni, Ni Fu
  • Patent number: 9524209
    Abstract: A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 20, 2016
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventors: Alessandro Minzoni, Ni Fu
  • Patent number: 9361180
    Abstract: Methods, systems and apparatus for storing data by an ECC memory are provided. In one aspect, when an ECC memory configured to be used for data blocks with a first data length is used for data blocks with a reduced second data length, a method includes storing at least one data block with the second data length in a data bit storage part of a storage array and storing parity bits generated for only one data block of the at least one data block according to a relevant encoding rule in a parity bit storage part of the storage array. When the at least one data block is two or more data blocks, one or more judgment bits, which indicate that the stored parity bits correspond to the only one data block, are stored in one or more storage bits of the parity bit storage part that are not occupied.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: June 7, 2016
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventors: Alessandro Minzoni, Ni Fu
  • Publication number: 20160124803
    Abstract: Methods, devices, and systems for storage device data access and/or storage device error correction are provided. In one aspect, a storage device data access method comprises generating a parity bit for data to be stored; generating a flag bit that expresses whether a data mask is present or absent in the data to be stored; storing the data, the flag bit, and the parity bit; reading out the data, the flag bit and the parity bit; determining whether the data mask is present or absent based on the read out flag bit; in response to determining that the flag bit expresses the absence of the data mask, detecting and correcting the data using the read out parity bit; otherwise, in response to determining that the flag bit expresses the presence of the data mask, performing no detection or correction on the data.
    Type: Application
    Filed: March 19, 2014
    Publication date: May 5, 2016
    Inventor: Alessandro MINZONI
  • Publication number: 20150121171
    Abstract: A computer memory access method includes: receiving external data with a prefetching length, the external data having an unmasked first data portion and a masked second data portion; writing the unmasked first data portion to a corresponding data storage unit of a computer memory by a writing unit and reading a third data portion corresponding to the masked second data portion from the data storage unit by a reading unit; producing modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion; generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and then writing the parity bits to a parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Alessandro MINZONI, Ni FU
  • Publication number: 20150121172
    Abstract: A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Alessandro MINZONI, Ni FU
  • Publication number: 20150121170
    Abstract: Methods, systems and apparatus for storing data by an ECC memory are provided. In one aspect, when an ECC memory configured to be used for data blocks with a first data length is used for data blocks with a reduced second data length, a method includes storing at least one data block with the second data length in a data bit storage part of a storage array and storing parity bits generated for only one data block of the at least one data block according to a relevant encoding rule in a parity bit storage part of the storage array. When the at least one data block is two or more data blocks, one or more judgment bits, which indicate that the stored parity bits correspond to the only one data block, are stored in one or more storage bits of the parity bit storage part that are not occupied.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Alessandro MINZONI, Ni FU
  • Patent number: 7990798
    Abstract: An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately connected to an m-bit data bus. The memory banks are classified into two groups, each group including a memory bank of each memory bank region. The memory module further includes a selection device connected to the memory banks and being responsive to selection bits. The selection device selects one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: August 2, 2011
    Assignee: Qimonda AG
    Inventors: Alessandro Minzoni, Werner Obermaier
  • Patent number: 7728648
    Abstract: A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: June 1, 2010
    Assignee: Qimonda AG
    Inventors: Alessandro Minzoni, Thilo Schaffroth
  • Publication number: 20090219032
    Abstract: A system and method for determining circuit functionality under varying external operating conditions. One embodiment provides a circuit for a given input signal. Internal signals are generated at internal nodes for the given input signal and the next set of external operating conditions. The internal signals are compared with internal reference signals to determine whether the integrated circuit is functional under the next set of external operating conditions. If the circuit is found functional under the next set of external operating conditions, then the internal reference signals are set equal to the internal signals, the initial set of external operating conditions are set equal to the next set of external operating conditions, and the above described method is repeated.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Applicant: QIMONDA AG
    Inventors: Alessandro Minzoni, Bin Wang
  • Publication number: 20090097348
    Abstract: An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately connected to an m-bit data bus. The memory banks are classified into two groups, each group including a memory bank of each memory bank region. The memory module further includes a selection device connected to the memory banks and being responsive to selection bits. The selection device selects one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 16, 2009
    Applicant: QIMONDA AG
    Inventors: Alessandro Minzoni, Werner Obermaier