Abstract: A clock controller for use with an off-chip driver and including a first delay element, a second delay element, a restore circuit, and an adjustment circuit. The clock controller includes a node receiving a reference clock represented by a least one clock signal. The first delay element is configured to delay one of the at least one clock signals by a first delay time, and the second delay element is configured to delay one of the at least one clock signals by a second delay time. The restore circuit is configured to provide at least a first output clock to the off-chip driver, wherein the off-chip driver provides output data based at least on the first output clock. The adjustment circuit is configured to adjust the first and second time delays to adjust edges of the first output clock such that output data from the off-chip driver aligns with edges of the reference clock, and to adjust the second delay time to maintain the first output clock at a desired duty cycle.

Abstract: A memory comprises a first circuit, a second circuit, and a latch. The first circuit is configured to provide a first signal indicating an earliest time valid data is available from a memory array in response to a read command. The second circuit is configured to provide a second signal indicating a latest time valid data is available from the memory array in response to the read command. The latch is configured to be connected to a data line coupled to the memory array in response to the first signal and disconnected from the data line in response to the second signal to latch data read from the memory array.

Abstract: A memory circuit comprises an enable circuit and a receiver. The enable circuit is configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level. The receiver is configured to be activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal.

Abstract: An output circuit including a first circuit configured to provide a first output signal, a second circuit configured to provide a second output signal, and a third circuit. The third circuit is configured to receive a third output signal that is based on the first output signal and the second output signal. The third circuit is configured to provide enable signals that turn on one of the first circuit and the second circuit and turn off the other of the first circuit and the second circuit based on the third output signal that is updated via the turned on one of the first circuit and the second circuit.

Abstract: A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.

Abstract: A delay locked loop comprises a circuit configured to receive a clock signal, divide the clock signal by two to provide a divided clock signal, and mirror with respect to the divided clock signal a fractional portion of a feedback delay remaining after dividing the feedback delay by a multiple of a cycle of the clock signal to provide a first signal.

Abstract: A circuit including a deskew circuit. The deskew circuit is configured to receive a first signal having a first edge delayed from a second edge of a second signal by a first delay and a third edge delayed from a fourth edge of the second signal by a second delay. The deskew circuit is configured to provide a third signal having a first deskewed edge delayed from the first edge by a third delay and a second deskewed edge delayed from the third edge by a fourth delay. The difference between the fourth delay and the third delay is substantially equal to the difference between the first delay and the second delay.

Abstract: The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may also have a second switching array, which emits an output signal, which when the first signal first has changed its state, changes its state in reaction to a change in the state of the first signal, and, when the second signal first has changed its state, changes its state in reaction to a change in the state of the first signal.

Abstract: A delay device, with a controllable delay time, has three circuit parts. The delay device is connected in series between an input connection for receiving an input clock signal and an output connection for outputting an output clock signal. The delay time is set based on a phase difference between the input clock signal and the output clock signal. The first circuit part reduces the frequency of the input clock signal and forwards a clock signal with a reduced frequency. The second circuit part delays the signal and forwards it to the third circuit part which uses the modified clock signal to generate the output clock signal which has a frequency matching that of the input clock signal. Since a low-frequency clock signal is processed in the second circuit part, problems relating to a signal change in a high-frequency input clock signal in a delay chain are avoided.

Abstract: A variable delay line comprises a first blender delay configured to provide a first signal, a second blender delay configured to provide a second signal complementary to the first signal, and a coarse delay configured to delay the first signal if an even number of coarse delay elements are selected and delay the second signal if an odd number of coarse delay elements are selected.

Abstract: The invention relates to a clock signal correction method, and to a clock signal input/output device into which a clock signal or a signal obtained therefrom is input and transmitted to a frequency divider, wherein a signal output by the frequency divider is transmitted to a signal integrator, and wherein a signal output by the signal integrator is transmitted to a first signal comparison circuit, wherein the signal output by the frequency divider is additionally transmitted to a second signal comparison circuit, and wherein the clock signal input/output device additionally comprises a signal input circuit for outputting a clock output signal as a function of a signal output by the first signal comparison circuit, and of a signal output by the second signal comparison circuit.

Abstract: The invention refers to a clock distortion detection method, and a clock distortion detector including a first input for receiving a first clock signal, a second input for receiving a second clock signal, and at least one mirror delay element.

Abstract: A blender circuit configured to receive a first signal having a first signal phase and a second signal having a second signal phase. The first and second signals have a similar frequency and the first and second signal phases are separated by a time delay. The blender circuit includes a first, second and third circuits. The first circuit is configured to receive the first signal and to generate a plurality of first intermediate signals that are independent of the time delay between the first and second signals. The second circuit is configured to receive the second signal and to generate a plurality of second intermediate signals that are independent of the time delay between the first and second signals. The third circuit is configured to receive the first plurality and second plurality of intermediate signals and to generate plurality of out signals. Each of the plurality of out signals have different signal phases that are spaced in time relative to each other.

Abstract: A memory device capable of performing a read operation includes: a memory array that stores data; and off-chip drivers that supply as an output of the memory device data retrieved from the memory array. At least one of the off-chip drivers includes: an enable circuit that generates an enable signal in response to a read enable signal received by the off-chip driver, wherein the enable circuit controls the timing of the enable signal in accordance with a timing signal supplied to the enable circuit; and a driver circuit that drives the data off the memory device in response to the enable signal.

Abstract: A combined receiver and latch circuit is configured to receive an external clock signal, an external reference voltage and an external command signal. The circuit includes first and second nodes, first and second control gates, and an output circuit. The first and second nodes are each configured to be precharged under the control of the clock signal. The first control gate is configured to receive the reference voltage. The second control gate configured to receive the command signal. The output circuit is coupled to the first and second nodes. The first and second nodes are alternatively discharged by the first and second control gates in response to the reference voltage and the command signal. The output circuit is configured to be latched upon the alternative discharge of the first and second node.

Abstract: A duty distortion detector comprises a first synchronous mirror delay configured to mirror a first signal with respect to a clock signal to provide a second signal, and a second synchronous mirror delay configured to mirror the second signal with respect to an inverted clock signal to provide the first signal.

Abstract: A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal and an inverted clock signal and to obtain a delay signal that indicates a time difference between transitions of the clock signal and the inverted clock signal. The second circuit is configured to receive the clock signal and the inverted clock signal and the delay signal and to delay the clock signal based on the delay signal to provide an output clock signal having substantially a 50% duty cycle.

Abstract: A delay locked loop comprises a circuit configured to receive a clock signal, divide the clock signal by two to provide a divided clock signal, and mirror with respect to the divided clock signal a fractional portion of a feedback delay remaining after dividing the feedback delay by a multiple of a cycle of the clock signal to provide a first signal.

Abstract: A memory circuit comprises an enable circuit and a receiver. The enable circuit is configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level. The receiver is configured to be activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal.

Abstract: A delay locked loop (DLL) according to the present invention includes a cycle time detector to determine the quantity of delay elements within a clock cycle and adjust a DLL counter controlling a DLL variable delay line to enable operation or locking in response to DLL overflow and underflow conditions. The cycle time detector includes a ring oscillator having a strong correlation between the oscillator period and the DLL delay elements. The output of the oscillator controls the counter to provide a new locking position for the DLL in the presence of overflow or underflow conditions. The oscillator is driven for an interval corresponding to the product of the external clock period and the quantity of delay elements in the ring oscillator. In effect, the delay of the DLL is adjusted to the preceding or succeeding external clock period to enable locking in response to overflow or underflow conditions.