Patents by Inventor Alexander Branover
Alexander Branover has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10474211Abstract: A data processing system includes a power manager for providing a power event depth signal in response to a power event request signal. A plurality of real-time clients is coupled to the power manager. Each real-time client includes a client buffer that has a plurality of entries for storing data. The real-time client also includes a register for storing a watermark threshold for the client buffer, as well as logic for providing an allow signal when a number of valid entries in the client buffer exceeds the watermark threshold. A power management state machine is coupled to each of the plurality of real-time clients. The power management state machine provides a power event start signal in response to all of the plurality of real-time clients providing respective allow signals.Type: GrantFiled: July 28, 2017Date of Patent: November 12, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Sonu Arora, Alexander Branover, Benjamin Tsien
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Publication number: 20190033939Abstract: A data processing system includes a power manager for providing a power event depth signal in response to a power event request signal. A plurality of real-time clients is coupled to the power manager. Each real-time client includes a client buffer that has a plurality of entries for storing data. The real-time client also includes a register for storing a watermark threshold for the client buffer, as well as logic for providing an allow signal when a number of valid entries in the client buffer exceeds the watermark threshold. A power management state machine is coupled to each of the plurality of real-time clients. The power management state machine provides a power event start signal in response to all of the plurality of real-time clients providing respective allow signals.Type: ApplicationFiled: July 28, 2017Publication date: January 31, 2019Applicant: Advanced Micro Devices, Inc.Inventors: Sonu Arora, Alexander Branover, Benjamin Tsien
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Patent number: 9360906Abstract: An interface couples a plurality of compute units to a power management controller. The interface conveys a power report for the plurality of compute units to the power management controller. The power management controller receives the power report, determines a power action for the plurality of compute units based at least in part on the power report, and transmits a message specifying the power action through the interface. The power action is performed.Type: GrantFiled: May 1, 2013Date of Patent: June 7, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Alexander Branover, Steven Kommrusch, Marvin Denman, Maurice Steinman
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Patent number: 9021209Abstract: A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.Type: GrantFiled: February 8, 2010Date of Patent: April 28, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B. Steinman
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Patent number: 8966305Abstract: Techniques are disclosed relating to managing power consumption and latencies for entry and exit of idle power states. In one embodiment, a processor includes a processing core configured to operate in a plurality of power states (e.g., C-states) that includes an operating power state and at least one idle power state. The processing core is also configured to operate in a plurality of performance states. The processor further includes a power management unit configured to receive a request from the processing core to enter the at least one idle power state. The power management unit is configured to select a first of the plurality of performance states (e.g., P-states) based on the requested idle power state. In one embodiment, the power management unit is further configured to cause the processing core to transition into the selected first performance state prior to entering the requested idle power state.Type: GrantFiled: June 30, 2011Date of Patent: February 24, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B. Steinman, John P. Petry
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Patent number: 8959372Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.Type: GrantFiled: June 17, 2013Date of Patent: February 17, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B Steinman, William L Bircher
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Publication number: 20140331069Abstract: An interface couples a plurality of compute units to a power management controller. The interface conveys a power report for the plurality of compute units to the power management controller. The power management controller receives the power report, determines a power action for the plurality of compute units based at least in part on the power report, and transmits a message specifying the power action through the interface. The power action is performed.Type: ApplicationFiled: May 1, 2013Publication date: November 6, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Steven Kommrusch, Marvin Denman, Maurice Steinman
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Patent number: 8862920Abstract: A method of regulating power states in a processing system may begin with a processor component reporting a present processor power state to an input-output hub, where the present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and, in response to receiving the present processor power state, establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state. The method continues by determining a present hub power state for the input-output hub, wherein depth of the present hub power state is less than or equal to depth of the lowest allowable hub power state.Type: GrantFiled: June 16, 2011Date of Patent: October 14, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B. Steinman
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Patent number: 8832485Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.Type: GrantFiled: April 1, 2013Date of Patent: September 9, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Norman M. Hack, Maurice B. Steinman, John Kalamatianos, Jonathan M. Owen
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Patent number: 8793512Abstract: An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold.Type: GrantFiled: October 29, 2010Date of Patent: July 29, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Samuel D. Naffziger
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Patent number: 8656198Abstract: A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.Type: GrantFiled: April 26, 2010Date of Patent: February 18, 2014Assignees: Advanced Micro Devices, ATI Technologies ULCInventors: Alexander Branover, Maurice B. Steinman, Anthony Asaro, James B. Fry
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Patent number: 8589629Abstract: A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.Type: GrantFiled: March 27, 2009Date of Patent: November 19, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Jonathan Owen, Guhan Krishnan, Carl D. Dietz, Douglas Richard Beard, William K. Lewchuk, Alexander Branover
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Publication number: 20130283078Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.Type: ApplicationFiled: June 17, 2013Publication date: October 24, 2013Inventors: Alexander Branover, Maurice B. Steinman, William L. Bircher
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Patent number: 8566628Abstract: A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.Type: GrantFiled: May 6, 2009Date of Patent: October 22, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B. Steinman, Ming L. So, Xiao Gang Zheng
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Patent number: 8484498Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.Type: GrantFiled: August 26, 2010Date of Patent: July 9, 2013Assignee: Advanced Micro DevicesInventors: Alexander Branover, Maurice Steinman, William L. Bircher
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Patent number: 8463973Abstract: A system includes one or more processor cores, and a voltage regulator that provides an operating voltage to the one or more processor cores in response to receiving a voltage identifier signal that is indicative of the operating voltage. The system also includes a power management unit that may provide a first voltage identifier signal corresponding to a first operating voltage in response to determining that the processor cores are operating in a first operating state in which the one or more processor cores may draw up to a maximum load current. The power management unit may also provide a second voltage identifier signal corresponding to a second operating voltage, which is less than the first operating voltage, in response to determining that the processor cores are operating in a second operating state in which the processor cores are incapable of an increase in load current above a predetermined amount.Type: GrantFiled: August 31, 2010Date of Patent: June 11, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Samuel D. Naffziger, Alexander Branover
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Patent number: 8447994Abstract: One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units.Type: GrantFiled: July 24, 2009Date of Patent: May 21, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Sebastien Nussbaum, Alexander Branover, John Kalamatianos
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Patent number: 8443209Abstract: A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.Type: GrantFiled: July 24, 2009Date of Patent: May 14, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Sebastien Nussbaum, Alexander Branover, John Kalamatianos
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Patent number: 8438416Abstract: A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.Type: GrantFiled: October 21, 2010Date of Patent: May 7, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Andrej Kocev, Alexander Branover
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Patent number: 8412971Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.Type: GrantFiled: May 11, 2010Date of Patent: April 2, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Norman M. Hack, Maurice B. Steinman, John Kalamatianos, Jonathan M. Owen