Patents by Inventor Alexander Erik Mericas
Alexander Erik Mericas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10169187Abstract: A performance monitor including a saturating counter provides a relative measure of event frequency without requiring a minimum polling rate or periodic reset to avoid or account for counter overflow. The saturating counter is incremented upon detection of an event and decremented if an event is not detected within a predetermined period. The period of detecting may be programmable and may be determined by real time clock, processor or instruction cycles. Multiple event types may be selected from for detection and input to a single counter, or alternatively multiple event counters may be provided for various event types. The saturating counter may additionally be periodically reset in a selected operating mode, in combination with the decrementing action performed on the counter.Type: GrantFiled: August 18, 2010Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkat Rajeev Indukuru, Alexander Erik Mericas
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Patent number: 9280438Abstract: A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.Type: GrantFiled: October 30, 2013Date of Patent: March 8, 2016Assignee: International Business Machines CorporationInventors: Venkat Rajeev Indukuru, Daniel Owen, Alexander Erik Mericas, John Fred Spannaus
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Patent number: 8832416Abstract: An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.Type: GrantFiled: May 24, 2007Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Wen-Tzer Thomas Chen, Venkat Rajeev Indukuru, Alexander Erik Mericas, Mysore Sathyanarayana Srinivas
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Publication number: 20140059334Abstract: A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.Type: ApplicationFiled: October 30, 2013Publication date: February 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkat Rajeev Indukuru, Daniel Owen, Alexander Erik Mericas, John Fred Spannaus
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Patent number: 8615742Abstract: A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.Type: GrantFiled: November 16, 2010Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Venkat Rajeev Indukuru, Daniel Owen, Alexander Erik Mericas, John Fred Spannaus
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Patent number: 8612730Abstract: A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.Type: GrantFiled: June 8, 2010Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Ronald P. Hall, Venkat Rajeev Indukuru, Alexander Erik Mericas, Balaram Sinharoy, Zhong Liang Wang
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Patent number: 8479184Abstract: An information handling system includes a memory, a processor, and an instruction tracking unit. The processor executes program code and, while the program code executes, the instruction tracking unit decodes a multi-purpose no-op instruction within the program code. In turn, the instruction tracking unit sends an interrupt to the processor, which invokes a profiling module to collect and store profiling data in a profiling buffer.Type: GrantFiled: August 24, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Richard William Doing, Venkat Rajeev Indukuru, Alexander Erik Mericas, Mauricio Jose Serrano, Zhong Liang Wang
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Patent number: 8234484Abstract: A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath, is marked (tagged) for monitoring by a performance monitoring unit. The progress of marked instructions is monitored by the performance monitoring unit, and various stall counters are triggered by the progress of the marked instructions and the instruction groups they form a part of. The stall counters count cycles to give an indication of when certain delays associated with particular instructions occur and how serious the delays are.Type: GrantFiled: April 9, 2008Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Venkat Rajeev Indukuru, Alexander Erik Mericas
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Publication number: 20120124560Abstract: A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkat Rajeev Indukuru, Daniel Owen, Alexander Erik Mericas, John Fred Spannaus
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Publication number: 20120054726Abstract: An information handling system includes a memory, a processor, and an instruction tracking unit. The processor executes program code and, while the program code executes, the instruction tracking unit decodes a multi-purpose no-op instruction within the program code. In turn, the instruction tracking unit sends an interrupt to the processor, which invokes a profiling module to collect and store profiling data in a profiling buffer.Type: ApplicationFiled: August 24, 2010Publication date: March 1, 2012Applicant: International Business Machines CorporationInventors: RICHARD WILLIAM DOING, VENKAT RAJEEV INDUKURU, ALEXANDER ERIK MERICAS, MAURICIO JOSE SERRANO, ZHONG LIANG WANG
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Publication number: 20120046912Abstract: A performance monitor including a saturating counter provides a relative measure of event frequency without requiring a minimum polling rate or periodic reset to avoid or account for counter overflow. The saturating counter is incremented upon detection of an event and decremented if an event is not detected within a predetermined period. The period of detecting may be programmable and may be determined by real time clock, processor or instruction cycles. Multiple event types may be selected from for detection and input to a single counter, or alternatively multiple event counters may be provided for various event types. The saturating counter may additionally be periodically reset in a selected operating mode, in combination with the decrementing action performed on the counter.Type: ApplicationFiled: August 18, 2010Publication date: February 23, 2012Applicant: International Business Machines CorporationInventors: Venkat Rajeev Indukuru, Alexander Erik Mericas
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Patent number: 8055809Abstract: A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.Type: GrantFiled: December 24, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Matthias Fertig, Tilman Gloekler, Ralph C. Koester, Alexander Erik Mericas, Thomas Pflueger, Daniel Becker
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Patent number: 7913123Abstract: An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.Type: GrantFiled: September 12, 2008Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Ra'ed Mohammad Al-Omari, Alexander Erik Mericas, William John Starke
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Publication number: 20100161867Abstract: A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.Type: ApplicationFiled: December 24, 2008Publication date: June 24, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthias Fertig, Tilman Gloekler, Ralph C. Koester, Alexander Erik Mericas, Thomas Pflueger
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Patent number: 7711994Abstract: An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.Type: GrantFiled: May 31, 2008Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Michael Stephen Floyd, Alexander Erik Mericas, Robert Dominick Mirabella
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Patent number: 7620801Abstract: A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value in the LFSR, a mark bit, indicating the instruction is a marked instruction, is sent with the instruction to an execution unit. Responsive to an indication from the performance monitor, the value in the LFSR is incremented prior to selecting a next instruction to mark. If the value equals a predetermined prime number of increments, the value is reset to all ones to avoid any harmonics with the code stream being executed. Upon receiving the marked instruction, the execution unit combines the marked bit with a selected event and reports the marked event to the performance monitor.Type: GrantFiled: February 11, 2005Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: James Wilson Bishop, Michael Stephen Floyd, Alexander Erik Mericas, Robert Dominick Mirabella, Dung Quoc Nguyen, Philip Lee Vitale
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Patent number: 7617385Abstract: A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed.Type: GrantFiled: February 15, 2007Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Venkat Rajeev Indukuru, Alexander Erik Mericas
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Publication number: 20090259830Abstract: A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath, is marked (tagged) for monitoring by a performance monitoring unit. The progress of marked instructions is monitored by the performance monitoring unit, and various stall counters are triggered by the progress of the marked instructions and the instruction groups they form a part of. The stall counters count cycles to give an indication of when certain delays associated with particular instructions occur and how serious the delays are.Type: ApplicationFiled: April 9, 2008Publication date: October 15, 2009Inventors: Venkat Rajeev Indukuru, Alexander Erik Mericas
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Publication number: 20090031173Abstract: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.Type: ApplicationFiled: September 9, 2008Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ra'ed Mohammad Al-Omari, Alexander Erik Mericas, William John Starke
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Publication number: 20090024878Abstract: An apparatus and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.Type: ApplicationFiled: August 29, 2008Publication date: January 22, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ra'ed Mohammad Al-Omari, Alexander Erik Mericas, William John Starke