Patents by Inventor Alexander Ishii

Alexander Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9041451
    Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 8659338
    Abstract: A resonant clock distribution network architecture is proposed that uses clock drivers of programmable size and reference clocks of programmable duty cycle to achieve a target clock rise time and clock amplitude with low energy consumption when operating in any one of multiple clock frequencies in resonant or non-resonant mode. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: February 25, 2014
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20140015585
    Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Application
    Filed: December 13, 2012
    Publication date: January 16, 2014
    Applicant: CYCLOS SEMICONDUCTOR, INC.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 8593183
    Abstract: An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: November 26, 2013
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 8502569
    Abstract: An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: August 6, 2013
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 8400192
    Abstract: An architecture for resonant clock distribution networks is proposed. This architecture allows for the energy-efficient operation of a resonant clock distribution network at multiple clock frequencies through the deployment of flip-flops that can be selectively enabled. The proposed architecture is primarily targeted at the design of resonant clock networks with integrated inductors and exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: March 19, 2013
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 8368450
    Abstract: An inductor architecture for resonant clock distribution networks is proposed. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture is primarily targeted at the design of integrated inductors and exhibits relatively low area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: February 5, 2013
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 8362811
    Abstract: A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 29, 2013
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 8358163
    Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 22, 2013
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 8339209
    Abstract: An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: December 25, 2012
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 7973565
    Abstract: A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: July 5, 2011
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Alexander Ishii, Marios C. Papaefthymiou
  • Publication number: 20110140753
    Abstract: A resonant clock distribution network architecture is proposed that uses clock drivers of programmable size and reference clocks of programmable duty cycle to achieve a target clock rise time and clock amplitude with low energy consumption when operating in any one of multiple clock frequencies in resonant or non-resonant mode. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Application
    Filed: October 12, 2010
    Publication date: June 16, 2011
    Applicant: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20110090018
    Abstract: An inductor architecture for resonant clock distribution networks is proposed. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture is primarily targeted at the design of integrated inductors and exhibits relatively low area overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 21, 2011
    Applicant: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20110090019
    Abstract: An architecture for resonant clock distribution networks is proposed. This architecture allows for the energy-efficient operation of a resonant clock distribution network at multiple clock frequencies through the deployment of flip-flops that can be selectively enabled. The proposed architecture is primarily targeted at the design of resonant clock networks with integrated inductors and exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 21, 2011
    Applicant: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20110084773
    Abstract: A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Applicant: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20110084736
    Abstract: An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Applicant: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20110084774
    Abstract: An architecture for resonant clock distribution networks is proposed. The proposed architecture allows for the energy-efficient operation of the resonant clock distribution network in conventional mode, so that it meets target specifications for the clock waveform. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to at-speed testing and to binning of semiconductor devices according to achievable performance levels.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Applicant: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20110084775
    Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Applicant: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Publication number: 20110084772
    Abstract: An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Applicant: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 6424622
    Abstract: A buffer management scheme for an ATM switch where the static and dynamic thresholds are applied appropriately at different levels to ensure efficient and fair usage of buffer memory. A novel dynamic threshold mechanism which, while ensuring fair sharing of memory, maximizes the overall memory utilization.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: July 23, 2002
    Assignee: NEC USA, Inc.
    Inventors: Ruixue Fan, Alexander Ishii, Brian Mark, Gopalakrishnan Ramamurthy, Qiang Ren