Patents by Inventor Alexander J. Yerman

Alexander J. Yerman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5570074
    Abstract: A transformer having a very low, predetermined leakage inductance includes an elongate dielectric laminate having two surfaces. A primary winding having a pattern conformal to the configuration of the laminate is disposed on one surface and extends substantially the length of the laminate. The laminate has at least one secondary winding disposed on its other surface. The laminate is rolled with a dielectric layer about a cylinder, and the primary and secondary windings are patterned such that the primary and secondary windings comprise interleaved winding layers with the dielectric layer disposed between each of the winding layers. The rolled laminate, dielectric layer, and windings are contained within a cylindrical magnetic pot core. The result is a transformer having tightly interleaved primary and secondary windings and, therefore, a very low leakage inductance.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: October 29, 1996
    Assignee: General Electric Company
    Inventors: Robert L. Steigerwald, Alexander J. Yerman, Waseem A. Roshen
  • Patent number: 5414401
    Abstract: A multi-pole magnetic component, such as an inductor, includes z-folded conductive film windings and a core having a plurality of pairs of spaced apart core posts extending between a base plate and a top plate of the core. The core includes an air gap that is distributed substantially evenly along the flux path. Magnetic flux flows through the core posts in a series manner so as to have an opposite flux direction in adjacent poles. Preferably, the air gap is determined such that the ratio of the distance between each adjacent core post and the distance between the base and top plates results in magnetic fields that are substantially tangential to the surface of the conductive film winding. Furthermore, the core posts are preferably shaped to have a larger cross sectional area at the base portion of the posts than at the top portion thereof. Alternatively, the core posts are attached to the bottom plate and are inserted into suitably shaped cut-out portions of the top plate.
    Type: Grant
    Filed: February 20, 1992
    Date of Patent: May 9, 1995
    Assignee: Martin Marietta Corporation
    Inventors: Waseem A. Roshen, Alexander J. Yerman
  • Patent number: 5291173
    Abstract: A high-frequency, low-profile transformer having at least one pair of magnetic poles includes a primary winding having a z-folded, continuous primary conductive film with a generally serpentine configuration disposed on a primary dielectric membrane and further includes a z-folded, continuous secondary winding constructed from a plurality of secondary conductive film portions disposed on a secondary dielectric membrane. Each of the secondary conductive film portions is configured to form a single continuous path enclosing each of the magnetic poles in such manner that each path encloses one pole of each pair of the magnetic poles of each adjacent layer of the secondary winding. Each path thus continues along a respective fold of the winding stack. The secondary winding layers are interleaved with the primary winding layers and electrically connected together.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: March 1, 1994
    Assignee: General Electric Co.
    Inventors: Alexander J. Yerman, Waseem A. Roshen
  • Patent number: 5206621
    Abstract: A transformer having a barrel winding comprised of flat conductive film conductors is provided with a repeatable winding configuration by employing a dielectric metal laminate as the winding material and by patterning both primary and secondary windings on the same dielectric membrane, thereby fixing the relative positions of the primary winding and secondary winding terminals and conductors.
    Type: Grant
    Filed: July 2, 1990
    Date of Patent: April 27, 1993
    Assignee: General Electric Company
    Inventor: Alexander J. Yerman
  • Patent number: 5179512
    Abstract: A resonant converter, including a transformer for separating a high-voltage (primary) side from a relatively low-voltage (secondary) side, has at least one synchronous rectifier and an auxiliary sense winding coupled to the gate thereof. The input capacitances of the synchronous rectifiers are reflected to the primary side and the secondary side by the square of the ratio of the number of auxiliary sense winding turns to the number of primary andsecondary winding turns, respectively, thereby reducing the required size of the discrete resonant capacitor. In one embodiment, a gate bias voltage approximately equal to the device threshold voltage is applied to the gate of the synchronous rectifiers. The auxiliary sense windings are etched into a conductive film pattern of the secondary windings. The auxiliary sense windings provide nearly identical secondary and gate drive voltages so that the synchronous rectifiers are gated substantially at the zero-voltage crossings of the secondary winding voltages.
    Type: Grant
    Filed: September 18, 1991
    Date of Patent: January 12, 1993
    Assignee: General Electric Company
    Inventors: Rayette A. Fisher, Robert L. Steigerwald, Alexander J. Yerman
  • Patent number: 5134770
    Abstract: A high-frequency transformer is constructed from a flexible circuit comprising a primary conductive film winding and one or more secondary conductive film windings disposed on a single dielectric membrane. The flexible circuit is folded to form a stack of primary winding layers interleaved with secondary winding layers and then inserted into a mangetic cup core. The flexible circuit is preferably patterned photolithographically.
    Type: Grant
    Filed: June 4, 1990
    Date of Patent: August 4, 1992
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, Khai D. Ngo
  • Patent number: 5126715
    Abstract: A folded conductive film winding transformer provides a plurality of poles and enables increased turns ratios or power handling capacity in structures which must meet severe height limitations.
    Type: Grant
    Filed: July 2, 1990
    Date of Patent: June 30, 1992
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, Waseem A. Roshen
  • Patent number: 5084958
    Abstract: A conductive film magnetic component such as an inductor or transformer includes a conductive film winding having a generally serpentine configuration when disposed in a plane. This film is folded to form a stack of layers with each "layer" comprising part of a winding turn and with successive "layers" connected at the folds via the continuous conductive film. The conductive film may be self-supporting and coated with a dielectric layer or may be disposed on a dielectric membrane. The film and membrane are preferably patterned photolithographically.
    Type: Grant
    Filed: January 25, 1991
    Date of Patent: February 4, 1992
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, Khai D. Ngo
  • Patent number: 5043859
    Abstract: A package for a two-switching-device half bridge circuit comprises an insulating substrate having first, second and third external power terminals along with control terminals bonded to the substrate. The power terminals are configured to provide a straight-through-the package current path from the first external power terminal to the second or common external power terminal and from the second or common external power terminal to the third external power terminal. The control terminals are preferably Kelvin terminal pairs in order to minimize feedback from the power current paths to the control circuits. The power devices are preferably bonded to the first external power terminal and the second external power terminal, respectively, with their connections respectively to the second power terminal and third power terminal substantially identical in order to provide power current paths through the package having substantially identical electrical and thermal impedances.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: August 27, 1991
    Assignee: General Electric Company
    Inventors: Charles S. Korman, Alexander J. Yerman, Sayed-Amr A. El-Hamamsy, Constantine A. Neugebauer
  • Patent number: 5017902
    Abstract: A conductive film magnetic component such as an inductor or transformer includes a conductive film winding having a generally serpentine configuration when disposed in a plane. This film is folded to form a stack of layers with each "layer" comprising part of a winding turn and with successive "layers" connected at the folds via the continuous conductive film. The conductive film may be self-supporting and coated with a dielectric layer or may be disposed on a dielectric membrane. The film and membrane are preferably patterned photolithographically.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: May 21, 1991
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, Khai D. T. Ngo
  • Patent number: 4959630
    Abstract: A high-frequency transformer is constructed from a flexible circuit comprising a primary conductive film winding and one or more secondary conductive film windings disposed on a single dielectric membrane. The flexible circuit is folded to form a stack of primary winding layers interleaved with secondary winding layers and then inserted into a magnetic cup core. The flexible circuit is preferably patterned photolithographically.
    Type: Grant
    Filed: August 7, 1989
    Date of Patent: September 25, 1990
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, Khai D. Ngo
  • Patent number: 4905075
    Abstract: A semiconductor hermetic package for semiconductor device comprises base, sidewall and cover members. Signals can be coupled between the enclosed devices and external devices by coupling means including conductive regions disposed in and through the package. Light pipes or conductive tracks and paths extending through the package can be used to couple the signals. A portion of the package can function as a grading resistance.
    Type: Grant
    Filed: December 21, 1988
    Date of Patent: February 27, 1990
    Assignee: General Electric Company
    Inventors: Victor A. K. Temple, Alexander J. Yerman
  • Patent number: 4829014
    Abstract: An additive process allowing discretionary interconnection of only the acceptable devices on a semiconductor wafer includes screen printing a polyimide layer over the wafer to form vias over all of the device contact pads on the wafer while coating the remainder of the wafer. The devices are then individually tested through the vias and, when a device is determined to be unacceptable according to predetermined specifications, the vias above that device are filled with polyimide. A layer of metal is next deposited over the entire wafer by evaporation and makes electrical contact with only the acceptable devices since the unacceptable devices have been blocked off. The metal layer is thereafter patterned to leave an interconnection pattern wherein only the acceptable devices on the wafer are electrically connected.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: May 9, 1989
    Assignee: General Electric Company
    Inventor: Alexander J. Yerman
  • Patent number: 4824716
    Abstract: An impermeable encapsulation system for integrated circuit chips utilizes a polyimide-siloxane block copolymer as an undercoat applied to the chip surface and an impermeable outer coat comprised either of a non-reactive metal, such as titanium, tantalum or aluminum, or an amorphous semiconductor material comprising silicon-boron. All of these materials may be effectively applied at temperatures sufficiently low to avoid damaging the chip.
    Type: Grant
    Filed: December 28, 1987
    Date of Patent: April 25, 1989
    Assignee: General Electric Company
    Inventor: Alexander J. Yerman
  • Patent number: 4816422
    Abstract: A method for fabricating a composite semiconductor from a plurality of substantially identical individual semiconductor devices formed on a common semiconductor wafer includes testing the devices on the wafer to generate a positional mapping of acceptable and non-acceptable devices, dividing the wafer into a plurality of areas of arbitrary size, connecting corresponding contact pads on only the acceptable devices within a given area to each other via common conductive paths which are supported on a dielectric film covering the pads, the film having appropriately located holes filled with conductive material to electrically couple the common conductive paths and the underlying contact pads of only the acceptable devices. The devices within a given area are intercoupled in a manner to form an operational array; single or multiple arrays may be coupled together to form a composite package having common external contacts and heat sink supports.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: March 28, 1989
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, Constantine A. Neugebauer
  • Patent number: 4809135
    Abstract: A ceramic chip carrier comprising a ceramic substrate and a copper lead frame directly bonded to the substrate, the lead frame being formed to provide leads in fringe regions beyond the edges of the substrate which are connected together by a removable rim and adapted to be suitably formed to make electrical and mechanical contact with the conductive runs on a printed circuit board.
    Type: Grant
    Filed: November 20, 1987
    Date of Patent: February 28, 1989
    Assignee: General Electric Company
    Inventor: Alexander J. Yerman
  • Patent number: 4764485
    Abstract: A method for producing a hole in a polymer film includes the steps of depositing a conductive layer onto the polymer film and irradiating a spot on the layer with a burst of focused laser energy at a level sufficient to form an opening in the film and, subsequently, plasma etching the film so as to form a hole of desired depth in the polymer film underlying the opening in the conductive layer. This method is particularly applicable to the formation of multichip intergrated circuit packages in which a plurality of chips formed in a semiconductor wafer are coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting selected chip contact pads via a deposited conductive layer which overlies the film and fills the holes.
    Type: Grant
    Filed: January 5, 1987
    Date of Patent: August 16, 1988
    Assignee: General Electric Company
    Inventors: James A. Loughran, James G. McMullen, Alexander J. Yerman
  • Patent number: 4716124
    Abstract: Power semiconductor devices are manufactured using a flexible metal tape carrier to facilitate automation of the manufacturing process. Control leads are fashioned from portions of the tape carrier, with a main portion of the tape carrier serving as a main current lead. The manufacturing process permits thorough electrical testing of a power semiconductor chip prior to incorporation into a relatively expensive power device package. In particular, the power chip can be tested at full-rated current, at least where the current is pulsed at a low duty cycle.
    Type: Grant
    Filed: August 20, 1986
    Date of Patent: December 29, 1987
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, James A. Loughran
  • Patent number: 4646129
    Abstract: Hermetic power chip packages are constructed in building block form to reduce the cost of electrical testing of power chips. The power chip packages utilized dielectric plates with metallic sheets bonded to the dielectric plates. Electric access to at least selected terminals of a power chip is gained through one of the dielectric plates by including holes through the plates which are filled with a conductive medium. One form of the hermetic package includes a gasket with a thermal expansion coefficient close to that of a dielectric plate of the hermetic package and thereby results in a high level of package durability even after repeated cycling of the package between widely differing hot and cold temperatures.
    Type: Grant
    Filed: June 11, 1986
    Date of Patent: February 24, 1987
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, Constantine A. Neugebauer
  • Patent number: 4635092
    Abstract: Power semiconductor devices are manufactured using a flexible metal tape carrier to facilitate automation of the manufacturing process. Control leads are fashioned from portions of the tape carrier, with a main portion of the tape carrier serving as a main current lead. The manufacturing process permits thorough electrical testing of a power semiconductor chip prior to incorporation into a relatively expensive power device package. In particular, the power chip can be tested at full-rated current, at least where the current is pulsed at a low duty cycle.
    Type: Grant
    Filed: June 4, 1984
    Date of Patent: January 6, 1987
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, James A. Loughran