Patents by Inventor Alexander Lidow

Alexander Lidow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9837438
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: December 5, 2017
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20170330898
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Application
    Filed: July 20, 2017
    Publication date: November 16, 2017
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. de Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20170317179
    Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.
    Type: Application
    Filed: July 20, 2017
    Publication date: November 2, 2017
    Inventors: Jianjun Cao, Alexander Lidow, Alana Nakata
  • Patent number: 9748347
    Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self- aligned ledges that extend toward the source contact and drain contact, respectively.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: August 29, 2017
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Alexander Lidow, Alana Nakata
  • Publication number: 20170162429
    Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan T. Strydom, Alana Nakata, Guangyuan Zhao
  • Patent number: 9607876
    Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 28, 2017
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan Strydom, Alana Nakata, Guang Y. Zhao
  • Patent number: 9583480
    Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 28, 2017
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20170047414
    Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 16, 2017
    Inventors: Jianjun Cao, Alexander Lidow, Alana Nakata
  • Patent number: 9331191
    Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 3, 2016
    Assignee: Efficient Power Conversion Corporation
    Inventors: Stephen L. Colino, Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20160111416
    Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
    Type: Application
    Filed: December 3, 2015
    Publication date: April 21, 2016
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20160086980
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 24, 2016
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20160035847
    Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Inventors: Jianjun Cao, Alexander Lidow, Alana Nakata
  • Patent number: 9214528
    Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: December 15, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao
  • Patent number: 9214399
    Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 15, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Patent number: 9214461
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: December 15, 2015
    Assignee: Efficient Power Coversion Corporation
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Patent number: 9171911
    Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 27, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao
  • Patent number: 8969918
    Abstract: An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 ? to 900 ?. In a preferred embodiment, the thickness is 600 ?.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: March 3, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao
  • Publication number: 20150034962
    Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20150028384
    Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 29, 2015
    Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
  • Publication number: 20150008442
    Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Inventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guang Yuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang, Ming-Kun Chiang, Jiali Cao