Patents by Inventor Alexander Saldanha
Alexander Saldanha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9922333Abstract: An advertising system identifies behaviors from user activity and associates the behaviors with a user profile. Advertisers provide the advertising system with information on conversion rates of users associated with user profiles. A behavioral model of user responses is built to identify the relative frequency of behaviors for increasing the response rate of ads. Incoming advertising requests are matched to modeled behaviors to determine an advertiser's interest in bidding on the ad placement.Type: GrantFiled: March 9, 2012Date of Patent: March 20, 2018Assignee: EXPONENTIAL INTERACTIVE, INC.Inventor: Alexander Saldanha
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Patent number: 9916589Abstract: An advertising system identifies behaviors from user activity and associates the behaviors with a user profile. Advertisers provide the advertising system with information on conversion rates of users associated with user profiles. A behavioral model of user responses is built to identify the relative frequency of behaviors for increasing the response rate of ads. Incoming advertising requests are matched to modeled behaviors to determine an advertiser's interest in bidding on the ad placement.Type: GrantFiled: March 9, 2012Date of Patent: March 13, 2018Assignee: EXPONENTIAL INTERACTIVE, INC.Inventors: Alexander Saldanha, Mikhail Faiguenblat
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Publication number: 20140324567Abstract: An advertising attribution system determines an attribution value for a set of advertising modalities associated with a conversion event. The modalities each provided an advertisement to a user who performed the conversion event. A conversion value associated with each of a plurality of modality subsets is determined representing the value to the advertiser of providing advertisements by the modalities in each modality subset. Based on the conversion value of each modality subset, a marginal value for each modality is determined for the set of modalities associated with the conversion event.Type: ApplicationFiled: July 7, 2014Publication date: October 30, 2014Inventors: Alexander Saldanha, Ron Berman, Keshore Vummarao
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Patent number: 8775248Abstract: An advertising attribution system determines an attribution value for a set of advertising modalities associated with a conversion event. The modalities each provided an advertisement to a user who performed the conversion event. A conversion value associated with each of a plurality of modality subsets is determined representing the value to the advertiser of providing advertisements by the modalities in each modality subset. Based on the conversion value of each modality subset, a marginal value for each modality is determined for the set of modalities associated with the conversion event.Type: GrantFiled: March 14, 2013Date of Patent: July 8, 2014Assignee: Abakus, Inc.Inventors: Alexander Saldanha, Ron Berman, Keshore Vummarao
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Publication number: 20130238422Abstract: An advertising system identifies behaviors from user activity and associates the behaviors with a user profile. Advertisers provide the advertising system with information on conversion rates of users associated with user profiles. A behavioral model of user responses is built to identify the relative frequency of behaviors for increasing the response rate of ads. Incoming advertising requests are matched to modeled behaviors to determine an advertiser's interest in bidding on the ad placement.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: EXPONENTIAL INTERACTIVE, INC.Inventor: Alexander Saldanha
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Publication number: 20130238425Abstract: An advertising system identifies behaviors from user activity and associates the behaviors with a user profile. Advertisers provide the advertising system with information on conversion rates of users associated with user profiles. A behavioral model of user responses is built to identify the relative frequency of behaviors for increasing the response rate of ads. Incoming advertising requests are matched to modeled behaviors to determine an advertiser's interest in bidding on the ad placement.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: EXPONENTIAL INTERACTIVE, INC.Inventors: Alexander Saldanha, Mikhail Faiguenblat
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Publication number: 20080126080Abstract: A method and system for converting plain text into structured data. Parse trees for the plain text are generated based on the grammar of a natural language, the parse trees are mapped on to instance trees generated based on an application-specific model. The best map is chosen, and the instance tree is passing to an application for execution. The method and system can be used both for populating a database and/or for retrieving data from a database based on a query.Type: ApplicationFiled: October 31, 2007Publication date: May 29, 2008Inventors: Alexander Saldanha, Patrick C. McGeer, Luca Carionl
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Patent number: 7324936Abstract: A method and system for converting plain text into structured data. Parse trees for the plain text are generated based on the grammar of a natural language, the parse trees are mapped on to instance trees generated based on an application-specific model. The best map is chosen, and the instance tree is passing to an application for execution. The method and system can be used both for populating a database and/or for retrieving data from a database based on a query.Type: GrantFiled: March 5, 2004Date of Patent: January 29, 2008Assignee: Ariba, Inc.Inventors: Alexander Saldanha, Patrick McGreer, Luca Carloni
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Patent number: 7013438Abstract: A technique to design deep sub-micron (DSM) integrated circuits is disclosed, in which global wire delays are minimized first, before performing logic synthesis. According to the present method, a designer performs layout of physical blocks by estimating an area for each block. After connecting the pins of the blocks with no timing constraints, each wire is assigned to a metal layer, based on length. The delay of each wire is minimized by inserting buffers at optimal distances. The blocks are then partitioned into “cores” and “shells.” The shells and cores are synthesized, and then recombined. This procedure greatly reduces the number of design iterations required to complete a design.Type: GrantFiled: November 1, 2001Date of Patent: March 14, 2006Assignee: Cadence Design Systems, Inc.Inventors: Alexander Saldanha, Joe Higgins, Amit Mehrotra
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Patent number: 7010767Abstract: A method/process for repeater insertion in the absence of timing constraints. Delays are optimized for multi-receiver and multi-layer nets and can be introduced in the early steps of design planning. It serves as a tool for interconnect prediction as well as planning. In the presented formulation, no restrictions are made on where the repeaters are added or what the topology of the net is. The tabulated results demonstrate improvement (speed ups) using the method/process of the present invention. The present invention runs in linear time and achieves better results that the existing dynamic programming formulation and other published heuristics. Polarity in a circuit design is corrected by traversing the circuit and carrying backwards a cost of fixing the polarity. On a subsequent traversal, buffers inserted fix the polarity.Type: GrantFiled: August 1, 2001Date of Patent: March 7, 2006Assignee: Cadence Design Systems, Inc.Inventors: Shauki Elassaad, Alexander Saldanha
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Publication number: 20040257207Abstract: A method/process for repeater insertion in the absence of timing constraints. Delays are optimized for multi-receiver and multi-layer nets and can be introduced in the early steps of design planning. It serves as a tool for interconnect prediction as well as planning. In the presented formulation, no restrictions are made on where the repeaters are added or what the topology of the net is. The tabulated results demonstrate improvement (speed ups) using the method/process of the present invention. The present invention runs in linear time and achieves better results that the existing dynamic programming formulation and other published heuristics. Polarity in a circuit design is corrected by traversing the circuit and carrying backwards a cost of fixing the polarity. On a subsequent traversal, buffers inserted fix the polarity.Type: ApplicationFiled: August 1, 2001Publication date: December 23, 2004Inventors: Shauki Elassaad, Alexander Saldanha
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Publication number: 20040172237Abstract: A method and system for converting plain text into structured data. Parse trees for the plain text are generated based on the grammar of a natural language, the parse trees are mapped on to instance trees generated based on an application-specific model. The best map is chosen, and the instance tree is passing to an application for execution. The method and system can be used both for populating a database and/or for retrieving data from a database based on a query.Type: ApplicationFiled: March 5, 2004Publication date: September 2, 2004Inventors: Alexander Saldanha, Patrick C. McGreer, Luca Carloni
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Patent number: 6725187Abstract: A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.Type: GrantFiled: June 12, 2000Date of Patent: April 20, 2004Assignee: Cadence Design Systems, Inc.Inventors: Szu-Tsung Cheng, Alexander Saldanha, Patrick C. McGeer, Patrick Scaglia
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Patent number: 6714902Abstract: A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behavior, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values.Type: GrantFiled: March 2, 2000Date of Patent: March 30, 2004Assignee: Cadence Design Systems, Inc.Inventors: Han-Hsun Chao, Rahul Razdan, Alexander Saldanha
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Patent number: 6714939Abstract: A method and system for converting plain text into structured data. Parse trees for the plain text are generated based on the grammar of a natural language, the parse trees are mapped on to instance trees generated based on an application-specific model. The best map is chosen, and the instance tree is passing to an application for execution. The method and system can be used both for populating a database and/or for retrieving data from a database based on a query.Type: GrantFiled: January 8, 2001Date of Patent: March 30, 2004Assignee: Softface, Inc.Inventors: Alexander Saldanha, Patrick C. McGeer, Luca Carloni
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Publication number: 20030167266Abstract: A method and system for converting plain text into structured data. Parse trees for the plain text are generated based on the grammar of a natural language, the parse trees are mapped on to instance trees generated based on an application-specific model. The best map is chosen, and the instance tree is passing to an application for execution. The method and system can be used both for populating a database and/or for retrieving data from a database based on a query.Type: ApplicationFiled: January 8, 2001Publication date: September 4, 2003Inventors: Alexander Saldanha, Patrick C. McGeer, Luca Carloni
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Patent number: 6077305Abstract: A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.Type: GrantFiled: December 16, 1998Date of Patent: June 20, 2000Assignee: Cadence Design Systems, Inc.Inventors: Szu-Tsung Cheng, Alexander Saldanha, Patrick C. McGeer, Patrick Scaglia
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Patent number: 5752000Abstract: A system and method increases discrete function simulator performance by creating a data structure that completely and accurately models a system of discrete function elements. A discrete function simulator simulates the system using the data structure. Sequential circuits are converted into blocks of combinational elements having latch variables stored to and read from memory. The simulator performance is dependent upon the number of system inputs and outputs and not on the number of discrete function elements in the circuit being simulated.Type: GrantFiled: August 2, 1994Date of Patent: May 12, 1998Assignee: Cadence Design Systems, Inc.Inventors: Patrick C. McGeer, Alexander Saldanha, Alberto Sangiovanni-Vincentelli
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Patent number: 5696692Abstract: A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method includes the steps of determining a set of gates in the circuit coupled to the first primary input lead, the set of gates coupled to a set of edges, determining the 1-controllability of each edge in the set of edges; providing a binary OR tree to the circuit; coupling the set of edges to the binary OR tree; providing an AND gate to the circuit; coupling the AND gate to the binary OR tree and to the first primary input lead; providing a binary AND tree to the circuit; uncoupling the first primary input leads from the set of gates; and coupling the binary AND tree to the AND gate, to the binary OR tree, and to the set of gates.Type: GrantFiled: April 24, 1995Date of Patent: December 9, 1997Assignee: Cadence Design Systems, Inc.Inventors: Alexander Saldanha, Patrick McGeer, Luciano Lavagno
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Patent number: 5682519Abstract: A method for generating a low-power circuit from a Shannon graph having a plurality of primary inputs, a plurality of nodes including parent and child nodes, a first end-terminal, and a second end-terminal, each of the plurality of nodes having output edges associated therewith, includes the steps of: substituting the plurality of nodes and associated output edges with a plurality of cells, one cell for each node and output edge associated therewith, each cell including a plurality of elements; coupling a cell substituted for a parent node to cells substituted for child nodes of the parent node; and bypassing particular elements of child nodes having only one parent node.Type: GrantFiled: April 24, 1995Date of Patent: October 28, 1997Assignee: Cadence Design Systems, Inc.Inventors: Alexander Saldanha, Patrick McGeer, Luciano Lavagno