Patents by Inventor Alexander Simpson

Alexander Simpson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6893968
    Abstract: A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: May 17, 2005
    Assignee: Infineon Technologies AG
    Inventors: Peter Lahnor, Alexander Simpson
  • Publication number: 20050014454
    Abstract: A semiconductive wafer having a layer of conductive material formed thereon is polished. The semiconductor wafer is rotated against an abrasive polishing pad. A solution is applied to the semiconductor wafer and to the abrasive polishing pad. The solution includes an etchant of the conductive material.
    Type: Application
    Filed: January 29, 2003
    Publication date: January 20, 2005
    Applicant: Infineon Technologies North America Corp.
    Inventors: Peter Wrschka, Alexander Simpson
  • Patent number: 6845340
    Abstract: A system and method for machining data management is provided. Vibration and operation data are gathered from a machine tool and sent to a processing unit. The processing unit defines operation-specific vibration profiles, and generates an operation-specific data line for each profile. The data lines are stored in a memory for later retrieval. An output device is used to retrieve the data lines and plot them over a time domain to create an operation-specific data matrix useful in manufacturing operations analysis.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: January 18, 2005
    Assignee: Ford Motor Company
    Inventors: Paul Charles Edie, Roderick Alexander Simpson, Ingrid Margrit Kaufman
  • Patent number: 6827635
    Abstract: A method and apparatus of planarizing substrates is disclosed. A planarizing web medium is prepared for planarizing substrates to reduce defect generation. The planarizing web has a planarizing region and preparing region defined thereon, wherein at least one portion of the preparing region is outside the planarizing region. The web medium is advanced to move one portion of the web out of the planarizing region and another portion into the planarizing region.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: December 7, 2004
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventors: Peter Lahnor, Olaf Kuehn, Andreas Roemer, Alexander Simpson
  • Publication number: 20040185756
    Abstract: A method and apparatus of planarizing substrates is disclosed. A planarizing web medium is prepared for planarizing substrates to reduce defect generation. The planarizing web has a planarizing region and preparing region defined thereon, wherein at least one portion of the preparing region is outside the planarizing region. The web medium is advanced to move one portion of the web out of the planarizing region and another portion into the planarizing region.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 23, 2004
    Inventors: Peter Lahnor, Olaf Kuehn, Andreas Roemer, Alexander Simpson
  • Publication number: 20040176015
    Abstract: A method of determining the endpoint of a planarizing process is disclosed. An endpoint detection signal is selectively sampled from at least one predetermined location within a planarizing region defined on a planarizing web. Planarization is stopped when the endpoint criterion based on the endpoint detection signal is detected.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 9, 2004
    Inventors: Peter Lahnor, Olaf Kuehn, Andreas Roemer, Alexander Simpson
  • Publication number: 20040176926
    Abstract: A system and method for machining data management is provided. Vibration and operation data are gathered from a machine tool and sent to a processing unit. The processing unit defines operation-specific vibration profiles, and generates an operation-specific data line for each profile. The data lines are stored in a memory for later retrieval. An output device is used to retrieve the data lines and plot them over a time domain to create an operation-specific data matrix useful in manufacturing operations analysis.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Inventors: Paul Charles Edie, Roderick Alexander Simpson, Ingrid Margrit Kaufman
  • Patent number: 6740539
    Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: May 25, 2004
    Assignees: International Business Machines Corporation, Infineon Technologies A.G.
    Inventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
  • Publication number: 20030190809
    Abstract: A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 9, 2003
    Inventors: Peter Lahnor, Alexander Simpson
  • Publication number: 20030153198
    Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 14, 2003
    Inventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
  • Patent number: 6570256
    Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: May 27, 2003
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
  • Patent number: 6569769
    Abstract: The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation. The processes of the invention are preferably characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate. The method reduces or eliminates the transfer of topographic variations to levels below the desired planarization level. The processes enable elimination of special endpoint detection techniques. The processes are also especially suitable for polishing interlevel dielectrics.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 27, 2003
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: Laertis Economikos, Alexander Simpson, Ravikumar Ramachandran
  • Publication number: 20030017642
    Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
    Type: Application
    Filed: July 20, 2001
    Publication date: January 23, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
  • Publication number: 20020197937
    Abstract: The invention provides fixed-abrasive chemical-mechanical polishing processes which are effective in rapidly reducing thickness of oxide layers, especially siliceous oxides. The processes of the invention are preferably characterized by at least one step involving simultaneous use of a fixed-abrasive polishing element and an aqueous liquid medium containing an abrasive. Where the original oxide layer has topographic variation, the thickness reduction technique of the invention may be preceeded by topography reduction step using a fixed-abrasive and an aqueous medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide layer on the substrate.
    Type: Application
    Filed: June 22, 2001
    Publication date: December 26, 2002
    Applicant: International Business Machines Corporation
    Inventors: Laertis Economikos, Alexander Simpson
  • Patent number: 6485355
    Abstract: The invention provides fixed-abrasive chemical-mechanical polishing processes which are effective in rapidly reducing thickness of oxide layers, especially siliceous oxides. The processes of the invention are preferably characterized by at least one step involving simultaneous use of a fixed-abrasive polishing element and an aqueous liquid medium containing an abrasive. Where the original oxide layer has topographic variation, the thickness reduction technique of the invention may be preceeded by topography reduction step using a fixed-abrasive and an aqueous medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide layer on the substrate.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: November 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Laertis Economikos, Alexander Simpson
  • Patent number: 6350692
    Abstract: A method for polishing a dielectric layer containing silicon provides a fluorine-based inorganic compound during a polishing process. The dielectric layer is polished in the presence of the fluorine based compound to accelerate a polishing rate of the dielectric layer.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: February 26, 2002
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Laertis Economikos, Ravikumar Ramachandran, Alexander Simpson
  • Patent number: 6294470
    Abstract: The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation. The processes of the invention are preferably characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate. The method reduces or eliminates the transfer of topographic variations to levels below the desired planarization level. The processes enable elimination of special endpoint detection techniques. The processes are also especially suitable for polishing interlevel dielectrics.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: September 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Laertis Economikos, Alexander Simpson
  • Patent number: 5120167
    Abstract: A boring apparatus comprises an elongate support body adapted to be rotatable by a machine tool spindle, a cutter mounting body releasably securable to the end of the support body remote from the machine tool spindle and is provided with a cutter guide which slidably receives a cutter therein which is constrained by the guide to be displaceable in an adjustment direction inclined to the rotational axis of the elongate support body. An adjustment member is disposed within the elongate support body and is movable along an axis substantially coaxial with the rotational axis of the elongate support body, and an interengaging coupling on the adjustment member and on the cutting tool is provided whereby movement of the adjustment member along its axis of motion induces movement of the cutting tool in its adjustment direction.
    Type: Grant
    Filed: July 25, 1991
    Date of Patent: June 9, 1992
    Assignee: Forth Tool & Valve Limited
    Inventor: Alexander Simpson