Patents by Inventor Alexandre Vaufredaz
Alexandre Vaufredaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8372728Abstract: The invention relates to a process for fabricating a multilayer structure that includes bonding a first wafer onto a second wafer, where the first wafer may have a chamfered edge and the bonding interface has an adhesion energy of less than or equal to 1 J/m2, and thinning the first wafer so as to form a transferred layer, where before thinning the first wafer, a step of trimming the edge of the first wafer is carried out using a grinding wheel having a working surface which comprises grit particles with an average size of greater than or equal to 800 mesh or less than or equal to 18 microns, and wherein the trimming step is carried out by lowering the grinding wheel at a rate of descent of greater than or equal to 5 microns per second, such that the descent of the grinding wheel into the first wafer continues to a distance from the bonding interface that is less than or equal to 30 ?m.Type: GrantFiled: March 1, 2011Date of Patent: February 12, 2013Assignee: SoitecInventor: Alexandre Vaufredaz
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Patent number: 8314007Abstract: A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed.Type: GrantFiled: November 10, 2010Date of Patent: November 20, 2012Assignee: SoitecInventor: Alexandre Vaufredaz
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Patent number: 8298916Abstract: The invention relates to a process for fabricating a multilayer structure comprising: bonding a first wafer onto a second wafer, at least the first wafer having a chamfered edge; and thinning the first wafer so as to form in a transferred layer, the thinning comprising a grinding step and a chemical etching step. After the grinding step and before the chemical etching step, a trimming step of the edge of the first wafer is carried out using a grinding wheel, the working surface of which comprises grit particles having an average size of less than or equal to 800-mesh or greater than or equal to 18 microns, the trimming step being carried out to a defined depth in the first wafer so as to leave a thickness of the first wafer of less than or equal to 35 ?m in the trimmed region.Type: GrantFiled: March 8, 2011Date of Patent: October 30, 2012Assignee: SoitecInventors: Alexandre Vaufredaz, Sebastien Molinari
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Patent number: 8158013Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).Type: GrantFiled: June 23, 2009Date of Patent: April 17, 2012Assignee: SoitecInventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
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Publication number: 20120015497Abstract: A method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion that is different from that of the first substrate. The method includes a step (S6) of molecular bonding the second substrate (110) on the first substrate (120) made of sapphire. The method also includes, prior to bonding the two substrates together, a step (S1) of stoving the first substrate (120) at a temperature that lies in the range 100° C. to 500° C.Type: ApplicationFiled: November 16, 2009Publication date: January 19, 2012Inventors: Gweltaz Gaudin, Mark Kennard, Matteo Piccin, Ionut Radu, Alexandre Vaufredaz
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Patent number: 8091601Abstract: The invention relates to equipment for carrying out a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).Type: GrantFiled: June 23, 2009Date of Patent: January 10, 2012Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
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Publication number: 20110230003Abstract: The invention relates to a process for fabricating a multilayer structure (130) comprising: bonding a first wafer onto a second wafer, at least the first wafer having a chamfered edge; and thinning the first wafer so as to form in a transferred layer, the thinning comprising a grinding step and a chemical etching step. After the grinding step and before the chemical etching step, a trimming step of the edge of the first wafer is carried out using a grinding wheel, the working surface of which comprises grit particles having an average size of less than or equal to 800 mesh or greater than or equal to 18 microns, the trimming step being carried out to a defined depth in the first wafer so as to leave a thickness of the first wafer of less than or equal to 35 ?m in the trimmed region.Type: ApplicationFiled: March 8, 2011Publication date: September 22, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Alexandre Vaufredaz, Sebastien Molinari
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Publication number: 20110230005Abstract: The invention relates to a process for fabricating a multilayer structure that includes bonding a first wafer onto a second wafer, where the first wafer may have a chamfered edge and the bonding interface has an adhesion energy of less than or equal to 1 J/m2, and thinning the first wafer so as to form a transferred layer, where before thinning the first wafer, a step of trimming the edge of the first wafer is carried out using a grinding wheel having a working surface which comprises grit particles with an average size of greater than or equal to 800 mesh or less than or equal to 18 microns, and wherein the trimming step is carried out by lowering the grinding wheel at a rate of descent of greater than or equal to 5 microns per second, such that the descent of the grinding wheel into the first wafer continues to a distance from the bonding interface that is less than or equal to 30 ?m.Type: ApplicationFiled: March 1, 2011Publication date: September 22, 2011Inventors: Alexandre Vaufredaz, Sebastien Molinari
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Publication number: 20110195560Abstract: The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate onto a sapphire substrate and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate. In accordance with the method, grinding is carried out using a wheel with a grinding surface that comprises abrasive particles having a mean dimension of more than 6.7 ?m; further, after grinding and before etching, the method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range of 150° C. to 170° C.Type: ApplicationFiled: November 19, 2009Publication date: August 11, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Gweltaz Gaudin, Alexandre Vaufredaz, Fleur Guittard
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Publication number: 20110151644Abstract: A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed.Type: ApplicationFiled: November 10, 2010Publication date: June 23, 2011Inventor: Alexandre Vaufredaz
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Publication number: 20090294072Abstract: The invention relates to equipment for carrying out a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).Type: ApplicationFiled: June 23, 2009Publication date: December 3, 2009Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
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Publication number: 20090261064Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).Type: ApplicationFiled: June 23, 2009Publication date: October 22, 2009Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frederic Metral
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Patent number: 7601271Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).Type: GrantFiled: February 17, 2006Date of Patent: October 13, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
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Publication number: 20070119812Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).Type: ApplicationFiled: February 17, 2006Publication date: May 31, 2007Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frederic Metral