Patents by Inventor Alexandre Vaufredaz

Alexandre Vaufredaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8372728
    Abstract: The invention relates to a process for fabricating a multilayer structure that includes bonding a first wafer onto a second wafer, where the first wafer may have a chamfered edge and the bonding interface has an adhesion energy of less than or equal to 1 J/m2, and thinning the first wafer so as to form a transferred layer, where before thinning the first wafer, a step of trimming the edge of the first wafer is carried out using a grinding wheel having a working surface which comprises grit particles with an average size of greater than or equal to 800 mesh or less than or equal to 18 microns, and wherein the trimming step is carried out by lowering the grinding wheel at a rate of descent of greater than or equal to 5 microns per second, such that the descent of the grinding wheel into the first wafer continues to a distance from the bonding interface that is less than or equal to 30 ?m.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 12, 2013
    Assignee: Soitec
    Inventor: Alexandre Vaufredaz
  • Patent number: 8314007
    Abstract: A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: November 20, 2012
    Assignee: Soitec
    Inventor: Alexandre Vaufredaz
  • Patent number: 8298916
    Abstract: The invention relates to a process for fabricating a multilayer structure comprising: bonding a first wafer onto a second wafer, at least the first wafer having a chamfered edge; and thinning the first wafer so as to form in a transferred layer, the thinning comprising a grinding step and a chemical etching step. After the grinding step and before the chemical etching step, a trimming step of the edge of the first wafer is carried out using a grinding wheel, the working surface of which comprises grit particles having an average size of less than or equal to 800-mesh or greater than or equal to 18 microns, the trimming step being carried out to a defined depth in the first wafer so as to leave a thickness of the first wafer of less than or equal to 35 ?m in the trimmed region.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: October 30, 2012
    Assignee: Soitec
    Inventors: Alexandre Vaufredaz, Sebastien Molinari
  • Patent number: 8158013
    Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: April 17, 2012
    Assignee: Soitec
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
  • Publication number: 20120015497
    Abstract: A method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion that is different from that of the first substrate. The method includes a step (S6) of molecular bonding the second substrate (110) on the first substrate (120) made of sapphire. The method also includes, prior to bonding the two substrates together, a step (S1) of stoving the first substrate (120) at a temperature that lies in the range 100° C. to 500° C.
    Type: Application
    Filed: November 16, 2009
    Publication date: January 19, 2012
    Inventors: Gweltaz Gaudin, Mark Kennard, Matteo Piccin, Ionut Radu, Alexandre Vaufredaz
  • Patent number: 8091601
    Abstract: The invention relates to equipment for carrying out a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
  • Publication number: 20110230003
    Abstract: The invention relates to a process for fabricating a multilayer structure (130) comprising: bonding a first wafer onto a second wafer, at least the first wafer having a chamfered edge; and thinning the first wafer so as to form in a transferred layer, the thinning comprising a grinding step and a chemical etching step. After the grinding step and before the chemical etching step, a trimming step of the edge of the first wafer is carried out using a grinding wheel, the working surface of which comprises grit particles having an average size of less than or equal to 800 mesh or greater than or equal to 18 microns, the trimming step being carried out to a defined depth in the first wafer so as to leave a thickness of the first wafer of less than or equal to 35 ?m in the trimmed region.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 22, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Alexandre Vaufredaz, Sebastien Molinari
  • Publication number: 20110230005
    Abstract: The invention relates to a process for fabricating a multilayer structure that includes bonding a first wafer onto a second wafer, where the first wafer may have a chamfered edge and the bonding interface has an adhesion energy of less than or equal to 1 J/m2, and thinning the first wafer so as to form a transferred layer, where before thinning the first wafer, a step of trimming the edge of the first wafer is carried out using a grinding wheel having a working surface which comprises grit particles with an average size of greater than or equal to 800 mesh or less than or equal to 18 microns, and wherein the trimming step is carried out by lowering the grinding wheel at a rate of descent of greater than or equal to 5 microns per second, such that the descent of the grinding wheel into the first wafer continues to a distance from the bonding interface that is less than or equal to 30 ?m.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 22, 2011
    Inventors: Alexandre Vaufredaz, Sebastien Molinari
  • Publication number: 20110195560
    Abstract: The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate onto a sapphire substrate and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate. In accordance with the method, grinding is carried out using a wheel with a grinding surface that comprises abrasive particles having a mean dimension of more than 6.7 ?m; further, after grinding and before etching, the method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range of 150° C. to 170° C.
    Type: Application
    Filed: November 19, 2009
    Publication date: August 11, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Gweltaz Gaudin, Alexandre Vaufredaz, Fleur Guittard
  • Publication number: 20110151644
    Abstract: A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed.
    Type: Application
    Filed: November 10, 2010
    Publication date: June 23, 2011
    Inventor: Alexandre Vaufredaz
  • Publication number: 20090294072
    Abstract: The invention relates to equipment for carrying out a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Application
    Filed: June 23, 2009
    Publication date: December 3, 2009
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
  • Publication number: 20090261064
    Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Application
    Filed: June 23, 2009
    Publication date: October 22, 2009
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frederic Metral
  • Patent number: 7601271
    Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: October 13, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
  • Publication number: 20070119812
    Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Application
    Filed: February 17, 2006
    Publication date: May 31, 2007
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frederic Metral