Abstract: A phase-locked loop is disclosed. The phase-locked loop includes a phase error detector, an event detector, a loop filter, and an oscillator. The phase error detector is configured to receive an input signal and a feedback signal and output a phase error signal. The event detector is configured to detect a loss of lock condition based on the phase error signal. The loop filter is configured to filter the phase error signal to generate a filtered control signal based on a first set of filter parameter values, and in response to the loss of lock condition, filter the phase error signal to generate the filtered control signal based on a second set of filter parameter values different from the first set of filter parameter values. The oscillator is configured to output an output signal having a phase that is based on the filtered control signal.

Abstract: A radiation particle strike detection system is disclosed. The radiation particle strike detection system includes a radiation particle detector and a controller coupled to the radiation particle detector. The radiation particle detector is overlayed on at least one surface of a payload that is sensitive to interaction with radiation particles. The radiation particle detector is configured to undergo a change in state responsive to a radiation particle strike at a location on the radiation particle detector. The controller is configured to 1) monitor a state of the radiation particle detector; 2) detect a radiation particle strike on the radiation particle detector based on a change in state of the radiation particle detector; and 3) determine a location and time of the radiation particle strike on the radiation particle detector based on the change in state of the particle detector.

Abstract: A radiation particle strike detection system is disclosed. The radiation particle strike detection system includes a radiation particle detector and a controller coupled to the radiation particle detector. The radiation particle detector is overlayed on at least one surface of a payload that is sensitive to interaction with radiation particles. The radiation particle detector is configured to undergo a change in state responsive to a radiation particle strike at a location on the radiation particle detector. The controller is configured to 1) monitor a state of the radiation particle detector; 2) detect a radiation particle strike on the radiation particle detector based on a change in state of the radiation particle detector; and 3) determine a location and time of the radiation particle strike on the radiation particle detector based on the change in state of the particle detector.

Abstract: A stress sensor is provided, including a substrate and a bridge circuit disposed thereon. The bridge circuit is coupled between an output node and a ground node. The bridge circuit includes a first and second branch, the first branch having a first resistor coupled to a tunable resistor at a first intermediate node. The second branch has a second resistor coupled to a variable reference resistor of value Rref at a second intermediate node, wherein the variable reference resistor is configured to sweep through a plurality of discrete values Rref. The bridge circuit also includes an amplifier having a positive input terminal coupled to the first intermediate node and a negative input terminal coupled to the second intermediate node. The amplifier is configured to generate a digital voltage output at the output node as a function of the mechanical stress applied to the substrate and of the value Rref.

Abstract: A buffer circuit for a radio frequency (RF) signal includes a single leg and a feedback mesh. The single leg is coupled between a voltage supply and ground. The single leg includes a pMOS FET and an nMOS FET, and an output terminal defined at drain terminals of the pMOS FET and the nMOS FET. The buffer circuit includes an input terminal capacitively coupled to gates of the pMOS FET and the nMOS FET. The input terminal is configured to receive the RF signal, and a buffered signal is provided on the output terminal. The feedback mesh is coupled to the output terminal and coupled to the gates of the pMOS FET and the nMOS FET. The feedback mesh includes a series-coupled inductive-resistive feedback impedance, and a resistive feedback impedance in parallel with the series-coupled inductive-resistive feedback impedance.

Abstract: A buffer circuit for a radio frequency (RF) signal includes a single leg and a feedback mesh. The single leg is coupled between a voltage supply and ground. The single leg includes a pMOS FET and an nMOS FET, and an output terminal defined at drain terminals of the pMOS FET and the nMOS FET. The buffer circuit includes an input terminal capacitively coupled to gates of the pMOS FET and the nMOS FET. The input terminal is configured to receive the RF signal, and a buffered signal is provided on the output terminal. The feedback mesh is coupled to the output terminal and coupled to the gates of the pMOS FET and the nMOS FET. The feedback mesh includes a series-coupled inductive-resistive feedback impedance, and a resistive feedback impedance in parallel with the series-coupled inductive-resistive feedback impedance.

Abstract: A clock data recovery circuit is disclosed. The clock data recovery circuit includes a bit stream data rate divider and a digital phase-locked loop including a linear phase detector. The bit stream data rate divider is configured to divide a frequency of a serial data stream by a designated division factor to generate a divided serial data stream. The linear phase detector is configured to compare phases of the divided serial data stream and a feedback signal within the digital phase-locked loop and output an UP signal associated with phase lagging and a DOWN signal associated with phase leading of the feedback signal versus the divided serial data stream. The digital phase-locked loop is configured to output a clock signal having a phase based on a digital difference between a digitized-UP signal derived from the UP signal and a digitized-DOWN signal derived from the DOWN signal.

Abstract: A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADCs, an open-loop clocking circuit, and a time-multiplexing circuit. The plurality of ADCs receive an analog input signal. Each ADC is configured to sample the analog input signal upon receipt of a respective clock signal. The open-loop clocking circuit receives a main clock signal having a reference frequency, and then divides the main clock signal into a sequential plurality of respective clock signals, each having a frequency lower than the reference frequency, and each triggered by one other respective clock signal starting from the main clock signal. The open-loop clocking circuit then distributes the plurality of respective clock signals to the plurality of ADCs. The time-multiplexing circuit is coupled to the plurality of ADCs and is configured to combine respective digital output signals from the plurality of ADCs into a time series.

Abstract: A self-optimizing circuit for a FD-SOI device includes a static biasing circuit, a dosimeter, a reference circuit, an amplifier, a voltage source, and a feedback circuit. The static biasing circuit supplies a first bias. The dosimeter includes a dosimeter FD-SOI device and generates a dosimeter voltage sensitive to parametric shifts in the primary FD-SOI device. The reference circuit supplies a reference voltage. The amplifier is coupled to the dosimeter and the reference circuit, and supplies a second bias at an output of the static biasing circuit, the second bias proportional to a difference between the dosimeter voltage and the reference voltage. The voltage source generates a drive voltage to which the first bias and the second bias are referenced. The feedback circuit regulates supply of the drive voltage to a well of the dosimeter FD-SOI device according to the first bias and the second bias.

Abstract: A stress sensor is provided, including a substrate and a bridge circuit disposed thereon. The bridge circuit is coupled between an output node and a ground node. The bridge circuit includes a first branch and a second branch, the first having a first resistor, R1, having a first orientation and coupled to a tuning resistor, Rtune, at a first intermediate node. The second branch includes a second resistor, R2, having a second orientation that is different from the first orientation, and coupled to a variable resistor, Rvar, at a second intermediate node. The bridge circuit includes an amplifier having a positive input terminal coupled to the second intermediate node, and a negative input terminal coupled to the first intermediate node. The amplifier generates a voltage output at the output node as a function of mechanical stress applied to the substrate. Rvar is non-linearly tunable based on the voltage output.

Abstract: A stress sensor is provided, including a substrate and a bridge circuit disposed thereon. The bridge circuit is coupled between an output node and a ground node. The bridge circuit includes a first branch and a second branch, the first having a first resistor, R1, having a first orientation and coupled to a tuning resistor, Rtune, at a first intermediate node. The second branch includes a second resistor, R2, having a second orientation that is different from the first orientation, and coupled to a variable resistor, Rvar, at a second intermediate node. The bridge circuit includes an amplifier having a positive input terminal coupled to the second intermediate node, and a negative input terminal coupled to the first intermediate node. The amplifier generates a voltage output at the output node as a function of mechanical stress applied to the substrate. Rvar is non-linearly tunable based on the voltage output.

Abstract: An integrated circuit counter includes a segmented thermometer coding counter architecture that reaches the thermodynamic energy minimum for a forward/reverse counting operation, requiring only one write or one erase operation per count so that energy consumption can be minimized, and circuit endurance maximized.

Abstract: A regulator circuit includes a voltage regulator having a stability control input and an output for providing a regulated output voltage, an amplifier circuit having an input for receiving an error voltage of the voltage regulator, and an output, and a control circuit having an input coupled to the output of the amplifier and an output coupled to the stability control input of the voltage regulator, such that the regulator stability is maximized while the error voltage is minimized. The voltage regulator includes an LDO voltage regulator, the amplifier circuit includes an operational amplifier circuit, and the control circuit includes a load-sensing or load-replicating circuit.

Abstract: A method of determining Integral Non-Linearity (INL) of an Analog-to-Digital Converter (ADC) is provided. The method includes providing an input signal to the ADC, phase-locking a clock signal of a clock of the ADC to the input signal, generating a plurality of samples at a sampled phase on the input signal for a plurality of sampled phases, applying averaging to the plurality of samples for each sampled phase to generate a reconstructed ADC output signal, and determining the INL of the ADC based on a comparison of the reconstructed ADC output signal to a theoretical ADC output signal.

Abstract: A radiation-hardened reference circuit includes a precision voltage reference circuit for generating a current-controlling voltage at first and second terminals, a driver circuit for receiving the current-controlling voltage at first and second terminals and for generating an output reference voltage, and a differential sampling circuit having first and second input terminals coupled to the first and second terminals of the voltage reference circuit, and first and second output terminals coupled to the first and second terminals of the driver circuit.

Abstract: An integrated circuit counter includes a segmented thermometer coding counter architecture that reaches the thermodynamic energy minimum for a forward/reverse counting operation, requiring only one write or one erase operation per count so that energy consumption can be minimized, and circuit endurance maximized.

Abstract: A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

Abstract: An analog-to-digital converter (ADC) includes at least first thru third ADC slices configured to sample input signal and transmit first thru third digitally converted values thereof, at least one reference ADC slice configured to sample input signal and transmit a digitally converted reference value, first thru third and reference registers coupled to first thru third and reference ADC slices, respectively, a delay register having an input and output, and configured to produce a sample time adjustment signal, where the sample time adjustment signal facilitates adjustment of a phase of a next time sampling of the input signal by the second ADC slice, and a plurality of computational circuit elements coupled to the input, output, and the registers, and configured to determine values of an error, an approximate time derivative of the input signal estimated from the third, second and first sampled time point, and the sample time adjustment signal.

Abstract: A regulator circuit includes a voltage regulator having a stability control input and an output for providing a regulated output voltage, an amplifier circuit having an input for receiving an error voltage of the voltage regulator, and an output, and a control circuit having an input coupled to the output of the amplifier and an output coupled to the stability control input of the voltage regulator, such that the regulator stability is maximized while the error voltage is minimized. The voltage regulator includes an LDO voltage regulator, the amplifier circuit includes an operational amplifier circuit, and the control circuit includes a load-sensing or load-replicating circuit.

Abstract: A voltage reference circuit is provided. A voltage reference circuit includes a bridge circuit having a first branch, a second branch, and an amplifier. The bridge circuit is coupled between a precision voltage reference (PVR) node and a ground node. The first branch includes a first resistor of value R1 coupled to a reference resistor of value Rref at a first intermediate node. The second branch includes a second resistor of value R1 coupled to a variable resistor of value Rvar at a second intermediate node. Rvar is non-linearly tunable based on the PVR. The amplifier includes a positive input terminal coupled to the second intermediate node and a negative input terminal coupled to the first intermediate node. The amplifier is configured to generate the PVR.