Abstract: A testing apparatus for testing a multiplicity of electronic devices, in particular integrated circuits, comprises means for two-fold processing of symbolic test data. In one mode, a fast pass/fail test may be executed by data. In one mode, a fast pass/fail test may be executed by once transforming the pass/fail test-related symbolic data into executable data and downloading them into a test data memory. Repeated pass/fail tests may then be executed. In the second mode, the symbolic test data are transformed and downloaded every time the test is performed, which makes execution slower, but allows modification and value tests.

Abstract: A testing apparatus for testing and handling a multiplicity of devices, in particular electronic components such as integrated circuits or boards, comprises a test executor with a multiplicity of hierarchical operating levels assigned to respective physical or logical entities. At each level except the lowest one, test level controllers are provided which include a pre-activity sequence of tasks, a call to a lower operating level, a return from said lower operating level, and a post-activity sequence of tasks. At the lowest level, device test processors execute the actual test.