Abstract: Techniques for a fixed-point back propagation implementation with advantages in speed, memory usage, and precision as compared with a floating-point implementation have hitherto been elusive. An example embodiment of a 16-bit fixed-point back propagation method that achieves a same accuracy as a double-precision, floating-point implementation, as measured by a word-error-rate (WER) of an acoustic adaptation application using one hour of audio data is disclosed. The WER for a speaker-independent model is 5.85%, compared with 5.34% for a double-precision floating-point implementation, and 5.33% for a 16-bit fixed-point implementation according to an example embodiment. Further, an average number of compute cycles for one backward propagation stage decreases from 166784 for a floating-point implementation to 30232 for a fixed-point implementation according to an example embodiment.

Abstract: Arrangements are described for reducing response latency in intelligent personal assistant applications. While receiving a user request, preemptive responses are automatically prepared for a received portion of the user request. Partial classification word candidates are generated for words in the received portion of the user request, and then a predictive component is applied to generate extended classification word candidates that include the partial classification word candidates and additional classification word candidates. A preliminary search is performed of the extended classification word candidates to prepare the preemptive responses. While the input request continues, the preemptive responses are updated, and when the input request ends, the prepared preemptive responses are used to respond to the user request.

Abstract: Arrangements are described for reducing response latency in intelligent personal assistant applications. While receiving a user request, preemptive responses are automatically prepared for a received portion of the user request. Partial classification word candidates are generated for words in the received portion of the user request, and then a predictive component is applied to generate extended classification word candidates that include the partial classification word candidates and additional classification word candidates. A preliminary search is performed of the extended classification word candidates to prepare the preemptive responses. While the input request continues, the preemptive responses are updated, and when the input request ends, the prepared preemptive responses are used to respond to the user request.

Abstract: Improvements in the fabrication of integrated circuits are driven by the decrease of the size of the features printed on the wafers. Current lithography techniques limits have been extended through the use of phase-shifting masks, off-axis illumination, and proximity effect correction. More recently, liquid immersion lithography has been proposed as a way to extend even further the limits of optical lithography. This invention described a methodology based on contact or proximity printing using a projection lens to define the image of the mask onto the wafer. As the imaging is performed in a solid material, larger refractive indices can be obtained and the resolution of the imaging system can be increased.

Abstract: An optical lithography method is disclosed that uses double exposure of a reusable template mask and a trim mask to fabricate regularly-placed rectangular contacts in standard cells of application-specific integrated circuits (ASICs). A first exposure of the reusable template mask with periodic patterns forms periodic dark lines on a wafer and a second exposure of an application-specific trim mask remove the unwanted part of the dark lines and the small cuts of the dark lines left form the rectangular regularly-placed contacts. All contacts are placed regularly in one direction while unrestrictedly in the perpendicular direction. The regular placement of patterns on the template mask enable more effective use of resolution enhancement technologies, which in turn allows a decrease in manufacturing cost and the minimum contact size and pitch.

Abstract: Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

Abstract: The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to accommodate the format of existing mask writer. The complexity of the correction after OPC can create some issues for vector-scan e-beam mask writing tools as very small slivers are created when the data is converted to the mask write tool format. Moreover the number of shapes created after fracturing is quite large and are not related to some important characteristics of the layout like for example critical areas. A new technique is proposed where the order of the OPC and fracturing steps is reversed. The fracturing step is done first in order to guarantee that no slivers are created and that the number of shapes is minimized. The shapes created can also follow the edges of critical zones so that critical and non-critical edges can be differentiated during the subsequent OPC step.

Abstract: A method and system is disclosed for allowing users to consolidate a large number electronic keys (for operating mechanical locks) in electronic key assemblies. These electronic keys are easily duplicated, added to, removed, backed up, or upgraded. The electronic key assemblies are also more resistant to tampering. The lock assembly and electronic key designs taught by the invention are customizable to meet various security needs. The lock assembly includes a transmitter and a receiver operatively coupled to an electronic circuit in communication with a store for keys. The electronic circuit is also coupled to the mechanical levers for operating the lock assembly. The electronic key assembly also has its transmitter, receiver, a control circuit and a user interface for selecting a particular electronic key password.

Abstract: An optical lithography method is disclosed that uses multiple exposures to decrease the minimum grid pitch of regularly spaced features. The desired grid pitch is selected to minimize the circuit area growth arising from the use of a grid constraint during layout. The desired grid is decomposed into at least two interleaved mask grids having a mask grid pitch that is greater than the desired grid pitch. Each mask grid is exposed to print a portion of the desired grid until the complete desired grid is printed to the die.

Abstract: A method and system is disclosed for allowing users to consolidate a large number electronic keys (for operating mechanical locks) in electronic key assemblies. These electronic keys are easily duplicated, added to, removed, backed up, or upgraded. The electronic key assemblies are also more resistant to tampering. The lock assembly and electronic key designs taught by the invention are customizable to meet various security needs. The lock assembly includes a transmitter and a receiver operatively coupled to an electronic circuit in communication with a store for keys. The electronic circuit is also coupled to the mechanical levers for operating the lock assembly. The electronic key assembly also has its transmitter, receiver, a control circuit and a user interface for selecting a particular electronic key password.

Abstract: A method for generating an optical proximity correction (OPC) model includes generating a set of correction rules for a wafer design containing at least one of lines and assist features, determining a set of corrections that need to be made over a range of sizes and spaces of the lines and assist features based on the set of correction rules, and creating an optical proximity correction model for correcting the wafer design based on the set of corrections.

Abstract: A technique is described, based on concepts of halftone printing, for controlling feature dimensions in a printed image at increments smaller than the smallest addressable unit of the template used to produce that image. Accordingly, photomasks may be fabricated to yield images with sizes differing from a nominal width by increments which are small fractions of the minimum template size or pixel size. A template fabricated according to this technique includes a feature having one or more edges, and a first array and a second array of shapes (protrusions or indentations) disposed on the edges. The first and second arrays have respective segmentation periods; the first and second segmentation periods are different. Each array is formed of a plurality of identical shapes repeating at every corresponding segmentation period, each shape having a predetermined length and a predetermined width.

Abstract: A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

Abstract: Optical proximity correction (OPC) and assist feature rules are generated using a process window (PW) analysis. A reference pitch is chosen and the mask bias is found that optimizes the process window. This can be done using standard process window analysis or through a weighted process window (WPW) analysis which accounts for focus and dose distributions that are expected in a real process. The WPW analysis gives not only the optimum mask bias, but also the center focus and dose conditions for the optimum process centering. A series of other pitches and mask biases are then analyzed by finding the common process window with the reference pitch. For the standard PW analysis, a common process window is found. For the WPW analysis, the WPW is computed at the center focus and dose conditions found for the reference pitch. If mask or lens errors are to be accounted for, then multiple structures can be included in the analysis.

Abstract: The present invention relates generally to a method for lithographically printing a mask pattern on a substrate, in particular a semiconductor substrate, wherein the mask pattern includes features with diverse pitches. These features may include device features such as vias or contact holes and lines in integrated circuits. The method comprises splitting the mask pattern into a plurality of masks, wherein one or more of the masks contains relatively tightly nested features and one or more of the masks contains relatively isolated features. Each of the plurality of masks is then successively exposed on a photoresist layer on the substrate. For each exposure, the exposure conditions, photoresist layer, other thin films layers, etching process, mask writing process, and/or mask pattern bias may be optimized for the tightly nested feature pattern or isolated feature pattern.

Abstract: A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed to form hollow polygonally-shaped clusters with a gap in the center. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure.

Abstract: The present invention relates generally to a method for lithographically printing a mask pattern on a substrate, in particular a semiconductor substrate, wherein the mask pattern includes features with diverse pitches. These features may include device features such as vias or contact holes and lines in integrated circuits. The method comprises splitting the mask pattern into a plurality of masks, wherein one or more of the masks contains relatively tightly nested features and one or more of the masks contains relatively isolated features. Each of the plurality of masks is then successively exposed on a photoresist layer on the substrate. For each exposure, the exposure conditions, photoresist layer, other thin films layers, etching process, mask writing process, and/or mask pattern bias may be optimized for the tightly nested feature pattern or isolated feature pattern.

Abstract: A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

Abstract: Optical proximity correction (OPC) and assist feature rules are generated using a process window (PW) analysis. A reference pitch is chosen and the mask bias is found that optimizes the process window. This can be done using standard process window analysis or through a weighted process window (WPW) analysis which accounts for focus and dose distributions that are expected in a real process. The WPW analysis gives not only the optimum mask bias, but also the center focus and dose conditions for the optimum process centering. A series of other pitches and mask biases are then analyzed by finding the common process window with the reference pitch. For the standard PW analysis, a common process window is found. For the WPW analysis, the WPW is computed at the center focus and dose conditions found for the reference pitch. If mask or lens errors are to be accounted for, then multiple structures can be included in the analysis.

Abstract: A method for reducing lens aberrations sensitivity and proximity effects of alternating phase shifted masks is described. The critical features of a chip design layout are first identified. Multiple, narrow phase regions and auxiliary phase transitions, which provide additional opaque features, are then formed alongside the critical features such that a grating pattern of substantially uniform pitch is printed. Together with a complementary trim mask, the circuit pattern so delineated has reduced sensitivity to lens aberrations and proximity effects.