Patents by Inventor Alfred Thomas Watson, III

Alfred Thomas Watson, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for executing instructions
    Patent number: 8082420
    Abstract: A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Miguel Comparan, Brent Francis Hilgart, Brian Lee Koehler, Eric Oliver Mejdrich, Adam James Muff, Alfred Thomas Watson, III
  • Optimized Graphical Calculation Performance by Removing Divide Requirements
    Publication number: 20090284524
    Abstract: By employing a scaled method for calculating the intersection of a ray with two bounding planes, divide operations may be avoided, which may result in fewer clock cycles and, possibly simplified processing logic.
    Type: Application
    Filed: May 14, 2008
    Publication date: November 19, 2009
    Inventors: Robert Allen Shearer, Alfred Thomas Watson, III
  • Method and Apparatus for Executing Instructions
    Publication number: 20090113181
    Abstract: A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
    Type: Application
    Filed: October 24, 2007
    Publication date: April 30, 2009
    Inventors: Miguel Comparan, Brent Francis Hilgart, Brian Lee Koehler, Eric Oliver Mejdrich, Adam James Muff, Alfred Thomas Watson, III