Patents by Inventor Ali Badiei

Ali Badiei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10650374
    Abstract: A system, method, and computer program product are provided for implementing high performance digital wallets. In use, a digital wallet with a plurality of transactions to process is identified. Further, a plurality of digital proxy-wallets are associated with the digital wallet. Additionally, digital currency from the digital wallet is allocated to the plurality of digital proxy-wallets. Moreover, the plurality of transactions are automatically processed in parallel utilizing the plurality of proxy-wallets such that the transactions are processed against the digital wallet.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: May 12, 2020
    Assignees: AMDOCS DEVELOPMENT LIMITED, AMDOCS SOFTWARE SYSTEMS LIMITED
    Inventors: Ajeet Singh, Naresh Chandra Miriyala, Ali Badiei, Peter Dimopoulos, Martin T J Balderstone
  • Patent number: 6928597
    Abstract: Digital circuitry is tested through effecting a paired data loop-back from a first buffered output to a first buffered input whilst within the circuitry executing at least part of the test through using a Built-In-Self-Test methodology. In particular, the loop-back is effected from the first buffered data output to a buffered control input, from a buffered control output to the first buffered data input, or both. Advantageously, the buffering is associated to executing a conversion between a digital full swing internal signal and an analog low swing external signal with respect to core circuitry of the digital circuitry.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: August 9, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Marcus Kuegler, Ali Badiei
  • Publication number: 20020053056
    Abstract: Digital circuitry is tested through effecting a paired data loop-back from a first buffered output to a first buffered input whilst within the circuitry executing at least part of the test through using a Built-In-Self-Test methodology. In particular, the loop-back is effected from the first buffered data output to a buffered control input, from a buffered control output to the first buffered data input, or both. Advantageously, the buffering is associated to executing a conversion between a digital full swing internal signal and an analog low swing external signal with respect to core circuitry of the digital circuitry.
    Type: Application
    Filed: April 3, 2001
    Publication date: May 2, 2002
    Inventors: Marcus Kuegler, Ali Badiei