Patents by Inventor Ali Sheikholeslami

Ali Sheikholeslami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11836651
    Abstract: According to an aspect of an embodiment, operations may include obtaining a first fixed temperature and a second fixed temperature of a replica exchange Markov Chain Monte Carlo (MCMC) process used to solve an optimization problem associated with a system, and obtaining a plurality of replicas of the system. The operations may also include obtaining a target swap acceptance probability with respect to swapping, during the replica exchange MCMC process, between replicas that correspond to adjacently ordered temperatures of a set of temperatures between the first fixed temperature and the second fixed temperature. The operations may include determining a respective average swap acceptance probability with respect to one or more respective adjacent pairs of temperatures. Further, the operations may include adjusting one or more of the variable temperatures based on a relationship between the target swap acceptance probability and each of one or more of the respective swap acceptance probabilities.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: December 5, 2023
    Assignees: FUJITSU LIMITED, THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Keivan Dabiri, Ali Sheikholeslami, Mehrdad Malekmohammadi, Hirotaka Tamura
  • Publication number: 20230350972
    Abstract: A storage unit stores some of a plurality of coupling coefficients stored in a storage device. A processing unit takes a plurality of first state variables among a plurality of state variables as a trial target set. The processing unit performs a process of reading a plurality of first coupling coefficients corresponding to a plurality of first pairs of the first state variables belonging to the trial target set from the storage device, storing the plurality of first coupling coefficients in the storage unit, and conducting, a plurality of times, a trial on whether to update the value of any first state variable belonging to the trial target set using the plurality of first coupling coefficients. The processing unit repeats change of the trial target set and the process, so as to target all the plurality of state variables in the trials.
    Type: Application
    Filed: March 30, 2023
    Publication date: November 2, 2023
    Applicants: Fujitsu Limited, THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Sigeng CHEN, Jeffrey Seth ROSENTHAL, Ali SHEIKHOLESLAMI, Hirotaka TAMURA, Satoshi MATSUBARA
  • Publication number: 20230169141
    Abstract: Operations may include identifying variables corresponding to an optimization problem, each variable having an initial value. The operations may include calculating an objective function value based on the initial value of each variable and a plurality of function value changes. Each function value change may be calculated based on a different variable value change, each variable value change corresponding to a respective change made to a different one of the variables. The operations may include selecting a subset of the variables based on the respective function value changes and corresponding variable value changes made to the respective initial values of the variables of the subset and generating a surrogate quadratic unconstrained binary optimization (QUBO) model using the subset. The operations may include determining a solution to the optimization problem including a set of solution values using the surrogate QUBO model, each of the solution values corresponding to a different variable.
    Type: Application
    Filed: April 30, 2021
    Publication date: June 1, 2023
    Applicants: FUJITSU LIMITED, THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Hirotaka TAMURA, Mehrdad MALEKMOHAMMADI, Keivan DABIRI, Ali SHEIKHOLESLAMI
  • Publication number: 20230110362
    Abstract: A first storage unit holds the values of discrete variables included in an evaluation function and the values of local fields for each replica. A second storage unit provided for each replica holds the values of corresponding discrete variables and local fields. A processing unit repeats, for each replica, a process of updating the value of any discrete variable, the value of the evaluation function, and the values of the local fields on the basis of a set temperature and the values of the local fields stored in the second storage unit, and after every predetermined number of iterations, performs resampling of population annealing. When a first replica is duplicated to create a second replica, the processing unit reads the values of the discrete variables and local fields of the first replica from the first storage unit and stores them in the second storage unit for the second replica.
    Type: Application
    Filed: October 5, 2022
    Publication date: April 13, 2023
    Applicant: Fujitsu Limited
    Inventors: Seyed Farzad MOUSAVI, Ali SHEIKHOLESLAMI
  • Patent number: 11562211
    Abstract: According to an aspect of an embodiment, operations may include obtaining a first matrix associated with an optimization problem associated with a system and obtaining a second matrix associated with the optimization problem. The operations may include obtaining a local field matrix that indicates interactions between the variables of the system as influenced by their respective weights. The operations may include updating the local field matrix. Updating the local field matrix may include performing arithmetic operations with respect to a first portion of the first matrix and a second portion of the second matrix that correspond to a third portion of the local field matrix that corresponds to the one or more variables. The operations may include updating an energy value of the system based on the updated local field matrix and determining a solution to the optimization problem based on the energy value.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 24, 2023
    Assignees: FUJITSU LIMITED, THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Mohammad Bagherbeik, Ali Sheikholeslami, Hirotaka Tamura, Kouichi Kanda
  • Publication number: 20220414184
    Abstract: A storage unit stores a flow matrix representing the flows between a plurality of entities to be assigned to a plurality of destinations, and a distance matrix representing the distances between the plurality of destinations. A processing unit calculates a first change in an evaluation function, which is to be caused by a first assignment change of exchanging the destinations of first and second entities among the plurality of entities, with vector arithmetic operations based on the flow and distance matrices, determines based on the first change whether to accept the first assignment change, and when determining to accept the first assignment change, updates an assignment state and updates the distance matrix by swapping the two columns or two rows (two columns in the example of FIG. 2) of the distance matrix corresponding to the first and second entities.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 29, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Mohammad BAGHERBEIK, Ali SHEIKHOLESLAMI
  • Publication number: 20220405616
    Abstract: According to an aspect of an embodiment, operations may include performing, based on weights and local field values associated with an optimization problem, a stochastic process with respect to changing a respective state of one or more variables that each represent a characteristic related to the optimization problem. The stochastic process may include performing trials with respect to one or more of the variables, in which a respective trial determines whether to change a respective state of a respective variable. The operations additionally may include determining an acceptance rate of state changes of the variables during the stochastic process and adjusting a degree of parallelism with respect to performing the trials based on the determined acceptance rate.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Applicants: FUJITSU LIMITED, THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Mohammad BAGHERBEIK, Ali SHEIKHOLESLAMI, Hirotaka TAMURA, Kouichi KANDA
  • Publication number: 20210326679
    Abstract: According to an aspect of an embodiment, operations may include obtaining a first matrix associated with an optimization problem associated with a system and obtaining a second matrix associated with the optimization problem. The operations may include obtaining a local field matrix that indicates interactions between the variables of the system as influenced by their respective weights. The operations may include updating the local field matrix. Updating the local field matrix may include performing arithmetic operations with respect to a first portion of the first matrix and a second portion of the second matrix that correspond to a third portion of the local field matrix that corresponds to the one or more variables. The operations may include updating an energy value of the system based on the updated local field matrix and determining a solution to the optimization problem based on the energy value.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 21, 2021
    Applicants: FUJITSU LIMITED, THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Mohammad BAGHERBEIK, Ali SHEIKHOLESLAMI, Hirotaka TAMURA, Kouichi KANDA
  • Publication number: 20210279652
    Abstract: According to an aspect of an embodiment, operations may include obtaining a first fixed temperature and a second fixed temperature of a replica exchange Markov Chain Monte Carlo (MCMC) process used to solve an optimization problem associated with a system, and obtaining a plurality of replicas of the system. The operations may also include obtaining a target swap acceptance probability with respect to swapping, during the replica exchange MCMC process, between replicas that correspond to adjacently ordered temperatures of a set of temperatures between the first fixed temperature and the second fixed temperature. The operations may include determining a respective average swap acceptance probability with respect to one or more respective adjacent pairs of temperatures. Further, the operations may include adjusting one or more of the variable temperatures based on a relationship between the target swap acceptance probability and each of one or more of the respective swap acceptance probabilities.
    Type: Application
    Filed: January 5, 2021
    Publication date: September 9, 2021
    Applicants: FUJITSU LIMITED, THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Keivan DABIRI, Ali SHEIKHOLESLAMI, Mehrdad MALEKMOHAMMADI, Hirotaka TAMURA
  • Patent number: 10718811
    Abstract: A jitter measurement circuit includes an addition circuit to add a digital rectangular signal to an adjustment signal generated by a circuit that generates a first error signal based on a phase difference between a first clock signal or a data signal on which the first clock signal is superimposed and a second clock signal and generates the adjustment signal by filtering the first error signal, and a calculation circuit to calculate a first correlation value for representing an autocorrelation of the first error signal when the rectangular signal is not added to the adjustment signal, and a second correlation value for representing the autocorrelation when the rectangular signal is added to the adjustment signal, based on the first error signal and a second error signal obtained by delaying the first error signal by a variable delay amount, and output the first correlation value and the second correlation value.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Joshua Liang, Ali Sheikholeslami, Sanroku Tsukamoto, Hirotaka Tamura, Hisakatsu Yamaguchi
  • Patent number: 10409322
    Abstract: A serial-parallel conversion circuit includes: a phase detector that outputs a first phase detection signal indicating whether a phase of a clock signal is advance or behind, a signal amplifying circuit that amplifies the first phase detection signal with a gain so as to output a second phase detection signal; a control loop that adjusts the phase of the clock signal based on the second phase detection signal; an autocorrelation circuit that generates an autocorrelation value based on the first phase detection signal and a set delay amount, and outputs an autocorrelation signal indicating the autocorrelation value; a gain adjusting circuit that adjusts the gain in such a manner that the autocorrelation value matches a target correlation value; and a delay-amount determination circuit that sets a delay amount corresponding to a peak value of an obtained autocorrelation value obtained when the autocorrelation value changes in an oscillatory manner.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 10, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Joshua Liang, Ali Sheikholeslami, Yuuki Ogata, Hirotaka Tamura
  • Patent number: 10225069
    Abstract: A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: March 5, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Wahid Rahman, Ali Sheikholeslami, Takayuki Shibasaki, Hirotaka Tamura
  • Publication number: 20180313895
    Abstract: A jitter measurement circuit includes an addition circuit to add a digital rectangular signal to an adjustment signal generated by a circuit that generates a first error signal based on a phase difference between a first clock signal or a data signal on which the first clock signal is superimposed and a second clock signal and generates the adjustment signal by filtering the first error signal, and a calculation circuit to calculate a first correlation value for representing an autocorrelation of the first error signal when the rectangular signal is not added to the adjustment signal, and a second correlation value for representing the autocorrelation when the rectangular signal is added to the adjustment signal, based on the first error signal and a second error signal obtained by delaying the first error signal by a variable delay amount, and output the first correlation value and the second correlation value.
    Type: Application
    Filed: April 24, 2018
    Publication date: November 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Joshua Liang, Ali Sheikholeslami, Sanroku Tsukamoto, Hirotaka TAMURA, Hisakatsu Yamaguchi
  • Publication number: 20180224885
    Abstract: A serial-parallel conversion circuit includes: a phase detector that outputs a first phase detection signal indicating whether a phase of a clock signal is advance or behind, a signal amplifying circuit that amplifies the first phase detection signal with a gain so as to output a second phase detection signal; a control loop that adjusts the phase of the clock signal based on the second phase detection signal; an autocorrelation circuit that generates an autocorrelation value based on the first phase detection signal and a set delay amount, and outputs an autocorrelation signal indicating the autocorrelation value; a gain adjusting circuit that adjusts the gain in such a manner that the autocorrelation value matches a target correlation value; and a delay-amount determination circuit that sets a delay amount corresponding to a peak value of an obtained autocorrelation value obtained when the autocorrelation value changes in an oscillatory manner.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 9, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Joshua Liang, Ali Sheikholeslami, Yuuki Ogata, Hirotaka TAMURA
  • Publication number: 20180227114
    Abstract: A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 9, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Wahid Rahman, Ali Sheikholeslami, Takayuki Shibasaki, Hirotaka TAMURA
  • Patent number: 9525444
    Abstract: A system may include a detector, a controller, a shuffler, and a processor. The detector may detect a signal. The controller may control the shuffler based upon the signal. The shuffler may shuffle a plurality of channels at the input of a plurality of processing elements of the processor based upon the signal. The processor may process the signal according to the plurality of channels as configured by the shuffler.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: December 20, 2016
    Assignee: Analog Devices Global
    Inventors: Hajime Shibata, Donald Paterson, Trevor Caldwell, Ali Sheikholeslami, Zhao Li
  • Publication number: 20150023455
    Abstract: A system may include a detector, a controller, a shuffler, and a processor. The detector may detect a signal. The controller may control the shuffler based upon the signal. The shuffler may shuffle a plurality of channels at the input of a plurality of processing elements of the processor based upon the signal. The processor may process the signal according to the plurality of channels as configured by the shuffler.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Applicant: ANALOG DEVICES TECHNOLOGY
    Inventors: Hajime Shibata, Donald Paterson, Trevor Caldwell, Ali Sheikholeslami, Zhao Li
  • Patent number: 7688610
    Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In other words, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: March 30, 2010
    Assignee: Mosaid Technologies Incorporated
    Inventors: Igor Arsovski, Ali Sheikholeslami
  • Publication number: 20090147556
    Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In other words, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.
    Type: Application
    Filed: February 10, 2009
    Publication date: June 11, 2009
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventors: Igor ARSOVSKI, Ali SHEIKHOLESLAMI
  • Patent number: 7511980
    Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: March 31, 2009
    Assignee: MOSAID Technologies Incorporated
    Inventors: Igor Arsovski, Ali Sheikholeslami