Patents by Inventor Ali Tasdighi

Ali Tasdighi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10789046
    Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.
    Type: Grant
    Filed: January 19, 2020
    Date of Patent: September 29, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10700695
    Abstract: Multipliers are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers. Generally, digital multipliers can operate at high speed with high precision, and synchronously. As the precision and speed of digital multipliers increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes solutions unsuitable for some ML and AI segments, including in portable, mobile, or near edge and near sensor applications. The present invention discloses embodiments of multipliers that arrange data-converters to perform the multiplication function, operating in mixed-mode (both digital and analog), and capable of low power consumptions and asynchronous operations, which makes them suitable for low power ML and AI applications.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 30, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10594334
    Abstract: Multipliers are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers. Generally, digital multipliers can operate at high speed with high precision, and synchronously. As the precision and speed of digital multipliers increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes solutions unsuitable for some ML and AI segments, including in portable, mobile, or near edge and near sensor applications. The present invention discloses embodiments of multipliers that arrange data-converters to perform the multiplication function, operating in mixed-mode (both digital and analog), and capable of low power consumptions and asynchronous operations, which makes them suitable for low power ML and AI applications.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 17, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10581448
    Abstract: A family of current mode analog to digital converters, or TiADC, utilizing methods, circuits, and apparatuses, are disclosed with the following benefits: (1) There are normal and random non-systematic mismatch between devices in silicon manufacturing, that introduce non-linearity in current mode analog to digital converter's, or iADC, reference network. The iADC's linearity is improved by utilizing a thermometer current mode signal conditioning method, SCM. Successive applications of the SCM effectuates a segmented current reference network to function like a thermometer network, which operates based on the function of summation. Having a TiADC with a thermometer reference network, where current segments are summed or accumulated incrementally, would inherently reduce the impact of statistical distribution of component's random mismatch on the iADC's non-linearity.
    Type: Grant
    Filed: February 3, 2019
    Date of Patent: March 3, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10560058
    Abstract: Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.
    Type: Grant
    Filed: October 27, 2018
    Date of Patent: February 11, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10536117
    Abstract: Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: January 14, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10491167
    Abstract: Methods, circuits, and apparatuses are disclosed that provide a buffer amplifier with lower output noise by narrow banding the amplifier. To reinvigorate the speed of the narrow-banded amplifier, a boost-on signal is initiated. The boost-on signal dynamically and rapidly injects a substantial current into the amplifier's bias current network to speed up its slew rate, when the amplifier's inputs get unbalanced when being subjected to a large transient differential input signal. Subsequently, after the amplifier regulate itself and as the amplifier's inputs approach substantial balance, a boost-off signal dynamically injects a slow and decaying current (that converges to the level of static steady-state bias current) into amplifier's bias circuitry, instead of turning off the boost current rapidly, which improves the amplifier's settling time.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: November 26, 2019
    Inventor: Ali Tasdighi Far
  • Patent number: 10411597
    Abstract: A family of bandgap embodiments are disclosed herein, capable of operating with very low currents and low power supply voltages, using neither any custom devices nor any special manufacturing technology, and fabricated on mainstream standard digital CMOS processes. As such, manufacturing cost can be kept low, manufacturing yields of digital CMOS system-on-a-chip (SOC) that require a reference can be kept optimal, and manufacturing risk can be minimized due to its flexibility with respect to fabrication process node-portability. Although the embodiments disclosed herein use novel techniques to achieve accurate operations with low power and low voltage, this family of bandgaps also uses parasitic bipolar junction transistors (BJT) available in low cost digital CMOS process to generate proportional and complementary to absolute temperature (PTAT and CTAT) voltages via the base-emitter voltage (VEB) of BJTs and scaling VEB differential pairs to generate the BJTs thermal voltage (VT).
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 10, 2019
    Inventor: Ali Tasdighi Far
  • Patent number: 10198022
    Abstract: A bias current topology with embodiments in current source, current reference, (pseudo bandgap) voltage reference, and bandgap voltage reference that operate at ultra low currents and low power supply voltages which may use main stream standard digital Complementary Metal-Oxide-Semiconductor (CMOS) processes. The bias current topology uses chiefly a self cascode (SC), whose active resistor MOSFET is paced in series with the gate input of the MOSFETs that help generate the proportional to absolute temperature (PTAT) voltage that is applied to the active resistor MOSFET to produce a bias current.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 5, 2019
    Inventor: Ali Tasdighi Far
  • Patent number: 10177713
    Abstract: Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 8, 2019
    Inventor: Ali Tasdighi Far
  • Patent number: 9921600
    Abstract: A bias current topology with embodiments in current source, current reference, (pseudo bandgap) voltage reference, and bandgap voltage reference that operate at ultra low currents and low power supply voltages which may use main stream standard digital Complementary Metal-Oxide-Semiconductor (CMOS) processes. The bias current topology uses chiefly a self cascode (SC), whose active resistor MOSFET is paced in series with the gate input of the MOSFETs that help generate the proportional to absolute temperature (PTAT) voltage that is applied to the active resistor MOSFET to produce a bias current.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 20, 2018
    Inventor: Ali Tasdighi Far
  • Patent number: 9780652
    Abstract: A family of bandgap embodiments are disclosed herein, capable of operating with very low currents and low power supply voltages, using neither any custom devices nor any special manufacturing technology, and fabricated on mainstream standard digital CMOS processes. As such, manufacturing cost can be kept low, manufacturing yields of digital CMOS system-on-a-chip (SOC) that require a reference can be kept optimal, and manufacturing risk can be minimized due to its flexibility with respect to fabrication process node-portability. Although the embodiments disclosed herein use novel techniques to achieve accurate operations with low power and low voltage, this family of bandgaps also uses parasitic bipolar junction transistors (BJT) available in low cost digital CMOS process to generate proportional and complementary to absolute temperature (PTAT and CTAT) voltages via the base-emitter voltage (VEB) of BJTs and scaling VEB differential pairs to generate the BJTs thermal voltage (VT).
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: October 3, 2017
    Inventor: Ali Tasdighi Far
  • Patent number: 9519304
    Abstract: A bias current topology with embodiments in current source, current reference, (pseudo bandgap) voltage reference, and bandgap voltage reference that operate at ultra low currents and low power supply voltages which may use main stream standard digital Complementary Metal-Oxide-Semiconductor (CMOS) processes. The bias current topology uses chiefly a self cascode (SC), whose active resistor MOSFET is paced in series with the gate input of the MOSFETs that help generate the proportional to absolute temperature (PTAT) voltage that is applied to the active resistor MOSFET to produce a bias current.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: December 13, 2016
    Inventor: Ali Tasdighi Far
  • Patent number: 6122284
    Abstract: In the preferred embodiment, the outputs of a plurality of analog signal generators are connected to a single wire (the analog bus). Each analog signal generator is addressable by a unique code provided to its respective address input terminals. A host controller selectively addresses only one of the analog signal generators such that an output of only one of the analog signal generators is applied to the analog bus at a time. In this manner, a single wire may be used to transmit a plurality of analog signals to a receiver. In one embodiment, the receiver is a MUX having an output connected to an ADC.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: September 19, 2000
    Assignee: Telcom Semiconductor, Inc.
    Inventors: Ali Tasdighi, Joseph J. Judkins, III, Chuong Nguyen, Donald E. Alfano
  • Patent number: 6054823
    Abstract: An apparatus for sensing the rotation of a brushless DC fan includes the fan and a sense/driver circuit and a capacitance. The sense/driver circuit is coupled to the fan to receive a sense input signal including a fluctuating electrical effect caused by fan commutation events. The sense/driver circuit processes the sense input signal to generate a sense output signal indicative of fan operation. The sense/driver circuit includes an integrated circuit. The integrated circuit includes a sense input pin, a ground return pin, a driver circuit, an integrated filter portion, a filter pin and a level detecting circuit. The capacitance is coupled to the filter pin to provide a filter with the integrated filter portion. The driver circuit includes a control terminal, a first current handling terminal coupled to the sense input pin and a second current handling terminal coupled to provide a ground return pat.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: April 25, 2000
    Assignee: Telcom Semiconductor, Inc.
    Inventors: Jerry Collings, Chuong Nguyen, Joseph James Judkins, III, Donald E. Alfano, Ali Tasdighi, Quoi V. Huynh, Sang T. Ngo
  • Patent number: 6005374
    Abstract: A programmable low dropout regulator includes an operational amplifier which is used both to provide a bandgap voltage and to drive an output load. In one embodiment implemented in an integrated circuit, external resistors are provided by the user to achieve a user-selected regulated voltage. In that embodiment, an input pin allows the user to select also internal resistors which provide a predetermined regulated voltage.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: December 21, 1999
    Assignee: TelCom Semiconductor, Inc.
    Inventor: Ali Tasdighi
  • Patent number: 5923208
    Abstract: A temperature-to-voltage converter includes a first circuit for developing a signal having a positive temperature coefficient and a second circuit for developing a signal having a voltage offset and a negative temperature coefficient. The converter also includes an adder circuit configured to subtract the negative-temperature-coefficient signal from the positive-temperature-coefficient signal. The resulting difference signal is a low voltage that exhibits linear temperature-to-voltage conversion, allowing the converter to be powered by a low operating voltage.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: July 13, 1999
    Assignee: Telecom Semiconductor, Inc.
    Inventors: Ali Tasdighi, Chuong Nguyen
  • Patent number: 5814995
    Abstract: A voltage detector is described herein which eliminates an entire operational amplifier or comparator from conventional voltage detectors. In one embodiment of such a voltage detector, a band gap reference generator is connected so as not to incorporate any feedback mechanism and where an off balance in the band gap reference generator is used to detect whether an input voltage falls below a threshold voltage. By eliminating the feedback path in the band gap reference generator, a comparator is eliminated. Other types of voltage detectors which provide a highly stable operation over a wide range of temperatures are described.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: September 29, 1998
    Assignee: TelCom Semiconductor, Inc.
    Inventor: Ali Tasdighi
  • Patent number: 5734260
    Abstract: A short-circuit protection circuit senses the output current of an output transistor to provide a control signal to a control transistor. The control transistor, in response to the control signal, varies an input voltage to an internal stage of an amplifier driving the output transistor, so as to cause the output transistor is switched off. A hysteresis resistor is coupled in series with an input terminal of the short circuit protection circuit, so as to prevent transient noise from switching off said output transistor.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: March 31, 1998
    Assignee: TelCom Semiconductor, Inc.
    Inventors: Ali Tasdighi, Phong Nguyen
  • Patent number: 5734291
    Abstract: An integrated circuit voltage converter containing a capacitive charge pump performing DC to DC conversion is disclosed which detects, either automatically or by an external signal, the onset of a low power consumption situation and switches to a low power consumption mode. In one embodiment, the low power consumption mode is accomplished by reducing the operating frequency of the charge pump. In another embodiment, the switching transistors used to switch the capacitors in the charge pump during a low power consumption mode are smaller than those transistors used to switch the capacitors during its normal operating mode. In another embodiment, the DC to DC converter switches back and forth between a high frequency (burst) mode and a low frequency (low power) mode at intervals. In another embodiment, a combination of the power reduction techniques is used. Various techniques for detecting when a low power consumption mode is appropriate are also described.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: March 31, 1998
    Assignee: TelCom Semiconductor, Inc.
    Inventors: Ali Tasdighi, Jerry M. Collings