Abstract: The method and apparatus of the present invention provide for a configurable radio front end topology that allows selectable operation in a single balanced mode and in a double balanced mode of operation. Logic associated with a baseband processor determines whether to operate in a single or double balanced mode of operation and produces the mode control signal to control selective coupling of circuit components according to the specified mode. Switching circuitry is used to switch a Balun in and out of connectivity. Further, a pair of LO polarity blocks are operable to determine the polarity of a differential LO received by associated mixers according to whether a single balanced or double balanced mode is in use.

Abstract: A circuit (e.g., a reconstruction filtering circuit) may include a single operational amplifier (op-amp) that is arranged to receive a voltage input and that is arranged to have a biasing of constant gmR, a first device capacitor that is operatively coupled to an output of the single op-amp, a first resistor that is operatively coupled to the first device capacitor, a second device capacitor that is operatively coupled to the first resistor, and a mirror device that is operatively coupled to the second device capacitor, where the mirror device is arranged to provide a feedback loop as a feedback input to the single op-amp and that is arranged to provide a current output.

Abstract: Methods and systems for gain control and power saving in broadband feedback low-noise amplifiers are disclosed and may include controlling gain, power and/or a noise figure by selectively enabling one or more of a plurality of gain stages by activating one or more of a plurality of pairs of switching transistors. Each of the gain stages may comprise complementary inverter pairs, with the gain of each of the gain stages binary weighted and stored in a lookup table. A feedback resistance coupled across the gain stages may be adjusted, and may comprise a plurality of individually addressable resistors, with the resistance binary weighted and stored in a lookup table. The adjusting of the feedback resistance may comprise switching one or more of a plurality of switching transistors, each connected in parallel with one of the individually addressable resistors, which may shunt one or more of the individually addressable resistors.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

Abstract: A calibration circuit measures the variation in a filter resistor within the analog domain of the envelope path of a polar transmitter and produces a digital value representative of that variation. A digital processor determines a digital control signal from the digital value that is used to compensate, in the digital domain of the envelope path, for the variation in the filter resistor in the analog domain.

Abstract: According to an example embodiment, an apparatus may be provided that is configurable to operate in either a separate power amplifier configuration or a combined power amplifier configuration.

Abstract: Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

Abstract: An apparatus comprising a plurality of switchable full step mixer unit cells, wherein each switchable full step unit cell is configured to, when the full step transceiver mixer unit cell is turned on, increase the gain experienced by an electronic signal by a full step increment, and wherein the step increment is substantially constant regardless of temperature; and at least one switchable partial step mixer unit cell configured to, when the partial step transceiver mixer unit is turned on, increase the gain experienced by the electronic signal by a predetermined step increment less than that of a full step, and wherein the partial step increment is substantially constant regardless of temperature

Abstract: In an envelope comparison embodiment, a delay calibrator produces a delay signal based on a comparison of a feedback signal and an envelope component of the transmitted signal. A down-converter produces the feedback signal from an outgoing modulated RF signal based on at least one local oscillation. Envelope detectors in the delay calibrator and the envelope signal path are operably coupled to a summing node that produces a delay error signal based on a temporal difference between the two envelopes. One embodiment includes phase detectors to detect and adjust the zero crossings of the feedback signal and the envelope signal path. As the delay mismatch between the envelope signal path and the phase signal path increases, the power spectrum increases in adjacent communication channels. A mask margin measurement technique measures the power level in an adjacent channel and adjusts the envelope path delay accordingly.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

Abstract: In an envelope comparison embodiment, a delay calibrator produces a delay signal based on a comparison of a feedback signal and an envelope component of the transmitted signal. A down-converter produces the feedback signal from an outgoing modulated RF signal based on at least one local oscillation. Envelope detectors in the delay calibrator and the envelope signal path are operably coupled to a summing node that produces a delay error signal based on a temporal difference between the two envelopes. One embodiment includes phase detectors to detect and adjust the zero crossings of the feedback signal and the envelope signal path. As the delay mismatch between the envelope signal path and the phase signal path increases, the power spectrum increases in adjacent communication channels. A mask margin measurement technique measures the power level in an adjacent channel and adjusts the envelope path delay accordingly.

Abstract: A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feedback oscillation. The charge pump is coupled to convert the difference signal into an up-signal or a down signal. The loop filter coupled to filter the up signal or the down signal to produce a control signal. The controlled oscillator is coupled to generate an output oscillation based on the control signal. The feedback divider is coupled to generate the feedback oscillation from the output oscillation based on a divider value. The loop filter includes a first resistor-capacitor circuit and a second resistor-capacitor circuit. The first resistor-capacitor circuit is calibrated using a first calibration technique and the second resistor-capacitor circuit is calibrated using a second calibration technique.

Abstract: A digital to analog conversion (DAC) module includes a digital to analog converter, a sample and hold circuit, and a switch module. The digital to analog converter is coupled to convert a digital signal into an analog signal. The sample and hold circuit is coupled to sample the analog signal to produce a sampled analog signal. The switch module is coupled to provide the analog signal as an output of the DAC module when the DAC module in a first mode and to output the analog signal to the sample and hold circuit when the DAC module in a second mode, wherein the sampled analog signal provides the output of the DAC module in the second mode.

Abstract: A differential amplifier is configured in a cascode configuration that includes input transistors that are connected to corresponding cascode transistors. The gates of the cascode transistors are tied together to form a common bias for the cascode devices. The input transistors of the differential amplifier receive a differential input signal that is amplified and outputted to an output circuit that is connected to the cascode transistors. The cascode devices require a bias voltage for proper operation. Preferably, the bias voltage puts the cascode devices into the saturation region. The gates of cascode devices are coupled together and connected to a bias terminal. In embodiments of the invention, the bias terminal is connected to another terminal of the chip to provide the bias for the cascode devices. This can include the input and output nodes if they have a well-defined and relatively fixed voltage.

Abstract: A digital to analog conversion (DAC) module includes a digital to analog converter, a sample and hold circuit, and a switch module. The digital to analog converter is coupled to convert a digital signal into an analog signal. The sample and hold circuit is coupled to sample the analog signal to produce a sampled analog signal. The switch module is coupled to provide the analog signal as an output of the DAC module when the DAC module in a first mode and to output the analog signal to the sample and hold circuit when the DAC module in a second mode, wherein the sampled analog signal provides the output of the DAC module in the second mode.

Abstract: A low-power programmable low-drop-out voltage regulator system and methods are presented. The regulator includes a local reference generator circuit that receives a voltage input signal and outputs a reference voltage signal, a buffer circuit that receives the reference voltage signal and outputs an output voltage signal, and a comparison device. The comparison device receives and compares the output voltage signal and an accurate reference voltage signal and outputs an adjustment signal to adjust the output voltage signal in the direction of a value of the accurate reference voltage signal. The regulator can include an attenuator circuit to attenuate the reference voltage signal. The output voltage signal can be regulated or programmed by adjusting the gain of the buffer circuit and/or the attenuator circuit. Current consumption can also be programmed by turning on or off one or more amplifier tiers located in the buffer circuit.

Abstract: Methods and systems for fast calibration to cancel phase feedthrough are disclosed and may comprise individually activating each of n binary-weighted cells utilizing a control signal in a power amplifier driver (PAD) and measuring the output signal, or offset, in response to a null signal applied to an input of each binary-weighted cell. This offset may be fed back, summed, and adjusted until the measured PAD output may be minimized. This calibrated offset may cancel phase feedthrough of the PAD, and the calibrated offset for each binary-weighted cell may be stored in a lookup table. The control signal may also be utilized for controlling the output power of the PAD by activating appropriate binary-weighted cells. For each of the 2n output powers, a calibrated offset is calculated utilizing a weighted sum of the stored offsets for the activated binary-weighted cells.

Abstract: A method for regulating a voltage in an integrated circuit device includes providing a first regulated output based upon a first voltage input range and subsequently receiving the first regulated output and providing a second regulated output based upon a second voltage input range of the first regulated output. A circuit is further provided that operates accordingly. Additionally, a clipper circuit is provided at the input to protect for over voltage conditions that may results, for example, from a charging battery to cause an output voltage of the battery to substantially exceed ordinary output voltage levels.

Abstract: Methods and systems for gain control and power saving in broadband feedback low-noise amplifiers are disclosed and may include controlling gain, power and/or a noise figure by selectively enabling one or more of a plurality of gain stages by activating one or more of a plurality of pairs of switching transistors. Each of the gain stages may comprise complementary inverter pairs, with the gain of each of the gain stages binary weighted and stored in a lookup table. A feedback resistance coupled across the gain stages may be adjusted, and may comprise a plurality of individually addressable resistors, with the resistance binary weighted and stored in a lookup table. The adjusting of the feedback resistance may comprise switching one or more of a plurality of switching transistors, each connected in parallel with one of the individually addressable resistors, which may shunt one or more of the individually addressable resistors.

Abstract: Methods and systems for robust single sideband LO generation are disclosed. Aspects of one method may include generating LO output signals where a VCO may generate a signal that may be used to generate a first pair of signals and a second pair of signals. The first pair of signals, with a frequency of 1.8 GHz, may be 90° out of phase With each other, and the second pair of signals, with a frequency of 800 MHz, may be 90° out of phase with each other. The second pair of signals may be linearly amplified and low-pass filtered. The filtered signals may be mixed with the first pair of signals to generate the LO output signals. A corner frequency for the low-pass filter may be substantially 1.5 times the frequency of a fundamental frequency for the signal to be filtered. Various embodiments of the invention may generate differential output signals, including the LO output signals.