Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

Abstract: Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.

Abstract: Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

Abstract: Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures. Other embodiments may be described or claimed.

Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures having gate cut offset, and methods of fabricating integrated circuit structures having gate cut offset, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires.

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.