Patents by Inventor Allen H. Gabor

Allen H. Gabor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10552569
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to mask structures and methods of manufacture. The method includes determining a plane through a frontside surface and a backside surface of a mask, each plane representing a flatness of the frontside surface and the backside surface, respectively; subtracting, using at least one computing device, a difference between the plane of the frontside surface and the plane of the backside surface to find a thickness variation; generating, using the at least one computing device, a fitting to fit the thickness variation; and subtracting, using the at least one computing device, the fitting from the thickness variation to generate a residual structure for collecting a residual flatness measurement.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christina Turley, Jed H. Rankin, Xuemei Chen, Allen H. Gabor, Timothy A. Brunner
  • Patent number: 10242952
    Abstract: Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Publication number: 20190080038
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to mask structures and methods of manufacture. The method includes determining a plane through a frontside surface and a backside surface of a mask, each plane representing a flatness of the frontside surface and the backside surface, respectively; subtracting, using at least one computing device, a difference between the plane of the frontside surface and the plane of the backside surface to find a thickness variation; generating, using the at least one computing device, a fitting to fit the thickness variation; and subtracting, using the at least one computing device, the fitting from the thickness variation to generate a residual structure for collecting a residual flatness measurement.
    Type: Application
    Filed: January 11, 2018
    Publication date: March 14, 2019
    Inventors: Christina TURLEY, Jed H. RANKIN, Xuemei CHEN, Allen H. GABOR, Timothy A. BRUNNER
  • Publication number: 20180331047
    Abstract: Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Patent number: 10043760
    Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Publication number: 20180061773
    Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.
    Type: Application
    Filed: October 26, 2017
    Publication date: March 1, 2018
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Patent number: 9859224
    Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Publication number: 20160358861
    Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 8, 2016
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Patent number: 9472506
    Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Publication number: 20160247766
    Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark.
    Type: Application
    Filed: February 25, 2015
    Publication date: August 25, 2016
    Inventors: David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Fee Li Lie, Stuart A. Sieg
  • Patent number: 9360858
    Abstract: Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christopher P. Ausschnitt, Timothy A. Brunner, Allen H. Gabor, Oleg Gluschenkov, Vinayan C. Menon
  • Patent number: 9046788
    Abstract: A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Allen H. Gabor, Wai-Kin Li
  • Patent number: 8847416
    Abstract: A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of target rectangle disposable within the target region.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christopher P. Ausschnitt, Nelson M. Felix, Allen H. Gabor
  • Patent number: 8673165
    Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sudharshanan Raghunathan, Sivananda Kanakasabapathy, Ryan O. Jung, Allen H Gabor, Sean D. Burns, Erin Catherine McLellan
  • Patent number: 8609322
    Abstract: A lithographic structure comprising: an organic antireflective material disposed on a substrate, and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiOx backbone, a chromophore, and a transparent organic group that is substantially transparent to 193 nm or 157 nm radiation. In combination, the organic antireflective material and the silicon antireflective material provide an antireflective material suitable for deep ultraviolet lithography. The invention is also directed to a process of making the lithographic structure.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Marie Angelopoulos, Katherina E. Babich, Sean D. Burns, Allen H. Gabor, Scott D. Halle, Arpan P. Mahorowala, Dirk Pfeiffer
  • Patent number: 8592110
    Abstract: A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Allen H. Gabor, Vinayan C. Menon
  • Patent number: 8507346
    Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Martin Burkhardt, Matthew E. Colburn, Allen H. Gabor, Oleg Gluschenkov, Scott D. Halle, Howard S. Landis, Helen Wang
  • Patent number: 8491984
    Abstract: A structure. The structure includes: a hole layer; a hole layer including a top hole layer surface, wherein the hole layer has a thickness in a first direction that is perpendicular to the hole layer surface; a bottom antireflective coating (BARC) layer on and in direct physical contact with the hole layer at the top hole layer surface; a photoresist layer on and in direct physical contact with the BARC layer, wherein a continuous hole in the first direction extends completely through the photoresist layer, the BARC layer, and the hole layer; and a polymerized hole shrinking region in direct physical contact with the photoresist layer at a lateral surface of the photoresist layer and with the hole layer at the top hole layer surface, wherein the hole shrinking region does not extend below the hole layer surface in a direction from the BARC layer to the hole layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Todd Christopher Bailey, Colin J. Brodsky, Allen H. Gabor
  • Patent number: 8455162
    Abstract: A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Allen H. Gabor, Vinayan C. Menon
  • Publication number: 20130089984
    Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sudharshanan Raghunathan, Sivananda Kanakasabapathy, Ryan O. Jung, Allen H. Gabor, Sean D. Burns, Erin Catherine Mclellan