Abstract: Described is a system for secure management of recovery data for data protection assets such as backup data and a backup application of a production backup system. The system may provide the ability to synchronize and secure critical recovery data of an isolated recovery environment. Accordingly, the system may reduce the breadth of potential cyber security attack vectors and increase the likelihood of efficiently recovering critical data and/or applications. To provide such capabilities, the system may only activate a data connection between a production system and a recovery system when synchronizing recovery data. In addition, the system may apply a retention lock to maintain a set of immutable copies of the recovery data and may restore the recovery data to a sandboxed environment where it may be tested and verified before being deployed to the production system as part of a recovery process.

Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

Abstract: A LED-circuit board affixing arrangement includes a circuit board and a LED affixed thereon. The circuit board has a first side, an opposed second side having a circuitry provide thereon, and a positioning hole formed on the circuit board. The LED includes an illuminating body having a head portion and a tail portion, and two legs extended therefrom to electrically connect to the circuitry, wherein the illuminating body is inserted into the positioning hole to hold the illuminating body on the board body at a position that the head portion is protruded from the first side of the circuit board and the tail portion is protruded from the second side of the circuit board. Therefore, the illuminating body of the LED is capable for producing lights throughout the head and tail portions thereof to provide a consequent light effect at the first and second sides of the circuit board.

Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

Abstract: A monolithic integrated circuit including a capacitor structure. In one embodiment the integrated circuit includes at least first and second levels of interconnect conductor for connection to a semiconductor layer and a stack of alternating conductive and insulative layers formed in vertical alignment with respect to an underlying plane. The stack is formed between the first and second levels of conductor. Preferably the stack includes a first conductive layer, a first insulator layer formed over the first conductive layer, a second conductive layer formed over the first insulative layer, a second insulator layer formed over the second conductive layer, and a third conductive layer formed over the second insulative layer, with the first and third conductive layers commonly connected.

Abstract: A LED-circuit board affixing arrangement includes a circuit board and a LED affixed thereon. The circuit board has a first side, an opposed second side having a circuitry provide thereon, and a positioning hole formed on the circuit board. The LED includes an illuminating body having a head portion and a tail portion, and two legs extended therefrom to electrically connect to the circuitry, wherein the illuminating body is inserted into the positioning hole to hold the illuminating body on the board body at a position that the head portion is protruded from the first side of the circuit board and the tail portion is protruded from the second side of the circuit board. Therefore, the illuminating body of the LED is capable for producing lights throughout the head and tail portions thereof to provide a consequent light effect at the first and second sides of the circuit board.

Abstract: The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.

Abstract: A structure and method for fabricating integrated circuits with improved electrical performance. The structure comprises electronic devices formed along a semiconductor surface, a first upper level of interconnect members over the semiconductor surface, a lower level of interconnect members formed between the semiconductor surface and the first upper level, and insulative material positioned to electrically isolate portions of the upper level of interconnect members from one another. The insulative material comprises a continuous layer extending from within regions between members of the upper interconnect level to within regions between members of the lower interconnect level and is characterized by a dielectric constant less than 3.9. The method begins with a semiconductor layer having electronic device regions thereon. A first insulative layer is deposited over the electronic device regions and a lower level of interconnect members is formed over the first insulative layer.

Abstract: A process (100) for forming a metal interconnect (102) in a semiconductor device (82) using a photoresist layer (20) having a thickness (T) of no more than 0.66 microns without forming a notch in the side (30) of the interconnect. A reactive ion etching process (118) used to remove portions of a metal layer (16) to form the interconnect includes a burst etch step (108) wherein a first high flow rate (48) of passivation gas is delivered, followed by a main metal etch step (110) wherein the flow rate of passivation gas is reduced to a second lower value.

Abstract: The present invention provides a method that includes defining a dummy gate structure comprising a spin on glass on a semiconductor substrate, forming a dielectric layer over the dummy gate structure, removing the dummy gate structure to form a gate opening within the dielectric layer, and forming a gate material comprising a metal within the gate opening.

Abstract: The present invention provides a method that includes defining a dummy gate structure comprising a spin on glass on a semiconductor substrate, forming a dielectric layer over the dummy gate structure, removing the dummy gate structure to form a gate opening within the dielectric layer, and forming a gate material comprising a metal within the gate opening.

Abstract: An integrated circuit device and method of making include an interconnect structure and a capacitor. The interconnect structure includes a metal line and a contact, and the capacitor includes upper and lower metal electrodes. The method includes forming a dielectric layer adjacent a semiconductor substrate, and simultaneously forming a first opening for the interconnect structure and a second opening for the capacitor, in the first dielectric layer. The method further includes selectively depositing a first conductive layer to fill the first opening to form the interconnect structure, and forming the upper and lower metal electrodes with a capacitor dielectric therebetween to form the capacitor in the second opening. The integrated circuit device provides a high-density capacitor having metal electrodes and which is compatible and integrated with dual damascene structures. As such, the capacitor is situated in a same level as a dual damascene interconnect structure.

Abstract: An apparatus for determining endpoint in the chemical mechanical polishing of a metal film using an acidic slurry includes a hydrogen sensor which senses the amount of hydrogen vapor being produced as a result of the reaction between the metal film and the acidic slurry. When the concentration of hydrogen vapor in the reaction area drops, endpoint is attained and the polishing operation may be terminated or otherwise adjusted. Hydrogen sensing elements include a palladium gate MOS transistor, expandable plastics and a tungsten oxide film.

Abstract: A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer.

Abstract: A method for stripping photoresist material (26) from a semiconductor substrate (16) avoids incorporation of sodium and other contaminant ions from a rework solvent. An oxygen and hydrogen plasma mixture strips the photoresist material without significant introduction of oxygen into the titanium nitride layer (24). Any oxidation of the titanium nitride is reversed by exposing the substrate to an oxygen-free, reducing plasma, such as a hydrogen-containing plasma. The titanium nitride layer is thereby much less susceptible to incorporation of contaminant ions in a subsequent cleaning with rework solvent than a layer which has been extensively oxidized during the plasma stripping process.

Abstract: The invention includes a process for the production of semiconductor devices comprising the steps of depositing a metal layer on a semiconductor substrate, depositing a hardmask layer on said metal layer, depositing a photoresist on said hardmask layer, patterning said photoresist, thereby exposing and patterning portions of said hardmask layer, etching said exposed portions of said hardmask layer with a hardmask etchant, thereby exposing and patterning portions of said metal layer, removing, or not, said photoresist, and etching said exposed portions of said metal layer with a metal etchant and semiconductor devices made by said process.