Abstract: Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.

Abstract: A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.

Abstract: Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.

Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Abstract: A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

Abstract: An apparatus and method of providing direct access to a non-volatile memory of a non-volatile memory device and detecting potential security violations are provided. A method for providing access to a non-volatile memory of a non-volatile memory device may include tracking a parameter related to a plurality of direct access transactions of the non-volatile memory. A threshold behavior pattern of the host activity may be determined based upon the tracked parameters. The direct access transactions may be reviewed to determine whether the threshold behavior pattern is exceeded.

Abstract: A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: A Data Storage Device (DSD) includes a Non-Volatile Memory (NVM) for storing data. A processor of the DSD receives a command from a host to access data in the NVM, and performs the command to access data in the NVM. The DSD further includes a host-trusted module functionally isolated from at least a portion of the DSD. The host-trusted module is configured to receive an instruction from the host, and perform an operation based on the instruction. According to one aspect, the operation includes a predetermined atomic operation to modify data stored in the NVM.

Abstract: The disclosure relates in some aspects to a controller of a data storage device, such as the controller of a solid state device (SSD) having non-volatile memory (NVM). In some aspects, the controller operates to prevent or reduce page faults in the host device. In one example, an outer mapping table of a set of page tables of a host device stores pointers to an inner mapping table in the SSD controller. The pointers are provided within memory access requests sent from the host to the SSD. The inner table maps the pointers to physical addresses in the SSD. The SSD detects page faults by identifying pointers that do not have corresponding entries in the inner table. The SSD allocates physical addresses to accommodate such access requests, then executes the requests on behalf of the host device. In this manner, the page fault is transparent to the host.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: An apparatus and method of providing direct access to a non-volatile memory of a non-volatile memory device and detecting potential security violations are provided. A method for providing access to a non-volatile memory of a non-volatile memory device may include tracking a parameter related to a plurality of direct access transactions of the non-volatile memory. A threshold behavior pattern of the host activity may be determined based upon the tracked parameters. The direct access transactions may be reviewed to determine whether the threshold behavior pattern is exceeded.

Abstract: Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.

Abstract: Technology is disclosed for reading non-volatile memory when a host does not need perfect data. By allowing the memory to return data with some errors, the data will be provided to the host much quicker. Therefore, in response to one or more host read commands, the memory system returns multiple copies of the data over time, progressively getting better so that later in time copies of the data have lower number of errors. The host decides when the error rate is good enough and stops the process (or ignores the rest of the results).

Abstract: Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.