Abstract: A circuit includes a plurality of logically identical clock modules which are all capable of driving the same clock output. The circuit has a selection input for selecting one of the clock modules for driving the clock output. After a change of the selection, a clock module just deselected awaits the completion of a period of the own clock signal before switching to deselection. The clock modules have a hold-off input which is coupled to a common signal line. A newly selected clock module switches to a selection state only after a beginning of a period of the own clock signal, provided that the selected clock module previously detects a signal on its hold-off input which indicates that all clock modules have deselected themselves. The common signal line is preferably coupled to the clock output, deselection being detected on the basis of the signal level which occurs after the beginning of the period after a change of the selection.

Abstract: A finite state machine that may receive actuator signals and has a plurality of elementary sequential logic elements fed by the actuator signals. Through various interconnections between the elements a first set of interconnected logic states is realized that are activated through combined occurrence of a particular predecessor state and an associated actuator signal. In various ones of said logic states a particular output signal is produced. Furthermore, the finite state machine has a subset of redundant logic states that are aggregated together with a particular operational by appropriate interconnections for collectively emulating the operational state in question.

Abstract: A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes:a. in a normal mode, all registers are accessible externally so that the memory may fulfill its standard function,b. in a scan-state, all the cited register constitute a synchronous shift register that may be serially written with a test pattern and serially read with a result pattern; in this way the memory may be subjected to a test according to the scan test principle,c. in a self test state the communication with the outer world is shut off, the address register counts through successive addresses, the memory is cycled through read-modify or read-modify-read operations, and the data read is conversed to a signature pattern for subsequent scan-out. In this way a quasi stand-alone test facility is realized. Various additional features may be implemented.