Patents by Inventor Alvaro Maury

Alvaro Maury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8872311
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, in one particularly advantageous embodiment, includes a multi layer etch stop located over a substrate, wherein the multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer. Located over the multi layer etch stop is a dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop. A conductive plug is typically located within the opening, wherein an insulative spacer is located between the conductive plug and the second silicon-rich nitride layer.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: October 28, 2014
    Assignee: Agere Systems Inc.
    Inventors: Nace Rossi, Alvaro Maury
  • Patent number: 7811944
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: October 12, 2010
    Assignee: Agere Systems Inc.
    Inventors: Nace Rossi, Alvaro Maury
  • Publication number: 20090108359
    Abstract: The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Applicant: Agere Systems Inc.
    Inventors: Nace Rossi, Alvaro Maury
  • Publication number: 20080079083
    Abstract: The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 3, 2008
    Applicant: Agere Systems Inc.
    Inventors: Nace Rossi, Alvaro Maury
  • Patent number: 7163438
    Abstract: A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: January 16, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Alvaro Maury, Jovin Lim, Nace Layadi, Sebastian Ouek
  • Patent number: 7005724
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: February 28, 2006
    Assignee: Agere Systems Inc.
    Inventors: Nace Rossi, Alvaro Maury
  • Patent number: 6984166
    Abstract: A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: January 10, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Alvaro Maury, Jovin Lim, Nace Layadi, Sebastian Quek
  • Publication number: 20050282372
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 22, 2005
    Applicant: Agere Systems Inc.
    Inventors: Nace Rossi, Alvaro Maury
  • Publication number: 20050277372
    Abstract: A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
    Type: Application
    Filed: August 22, 2005
    Publication date: December 15, 2005
    Inventors: Alvaro Maury, Jovin Lim, Nace Layadi, Sebastian Ouek
  • Publication number: 20050179116
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 18, 2005
    Applicant: Agere Systems Inc.
    Inventors: Nace Rossi, Alvaro Maury
  • Publication number: 20050179115
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, in one particularly advantageous embodiment, includes a multi layer etch stop located over a substrate, wherein the multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer. Located over the multi layer etch stop is a dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop. A conductive plug is typically located within the opening, wherein an insulative spacer is located between the conductive plug and the second silicon-rich nitride layer.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 18, 2005
    Applicant: Agere Systems Inc.
    Inventors: Nace Rossi, Alvaro Maury
  • Patent number: 6910907
    Abstract: The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: June 28, 2005
    Assignee: Agere Systems Inc.
    Inventors: Nace Layadi, Alvaro Maury
  • Publication number: 20050134857
    Abstract: A new method to monitor sheet resistance of a metal silicide layer in the manufacture of an integrated circuit device is achieved. The method comprises providing a metal silicide layer overlying an exposed silicon layer on a substrate. A thermal wave intensity signal is generated for the metal silicide layer by an optical measurement system. The optical measurement system comprises a first laser beam that is intensity modulated and a second laser beam. The first and second laser beams comprise different wavelengths. A dichroic mirror is used to combine the first and second laser beams and to project the first and second laser beams onto the metal silicide layer. A detector is used to gather the second laser beam reflected from the metal silicide layer and to generate a thermal wave intensity signal based on the reflected second laser beam. Sheet resistance of the metal silicide layer is calculated by a linear equation based on the thermal wave intensity signal.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Inventors: Alvaro Maury, Nace Layadi, Jovin Lim
  • Publication number: 20050106835
    Abstract: The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. The trench isolation structure, in accordance with the principles of the present invention, may include a substrate having a trench located therein, and an isolation material located within the trench, wherein the isolation material has no undercut at corners where the isolation material meets the substrate.
    Type: Application
    Filed: November 18, 2003
    Publication date: May 19, 2005
    Applicant: Agere Systems Inc.
    Inventors: Nace Layadi, Alvaro Maury
  • Publication number: 20050106919
    Abstract: The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.
    Type: Application
    Filed: November 18, 2003
    Publication date: May 19, 2005
    Applicant: Agere Systems Inc.
    Inventors: Nace Layadi, Alvaro Maury
  • Publication number: 20050026549
    Abstract: A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 3, 2005
    Inventors: Alvaro Maury, Jovin Lim, Nace Layadi, Sebastian Quek
  • Patent number: 6821886
    Abstract: A new method is provided for the creation of an adhesion/barrier layer over which a tungsten interconnect is created. The invention reduces metal extrusion and effects of pin-holes by dividing the process of barrier material of TiN deposition into phases, whereby after about half the thickness of the required layer of TiN has been deposited, an intermediate and very thin layer of Ti is deposited. After the thin layer of Ti has been deposited, the deposition of the barrier layer of TiN is continued to the point where the required thickness for the layer of TiN has been reached.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Nace Layadi, Alvaro Maury, Jovin Lim
  • Patent number: 6624039
    Abstract: The present invention provides a semiconductor device including large topography alignment marks, and a method of manufacture therefor. The method of manufacturing the semiconductor device includes forming an isolation trench and an alignment mark in a substrate to a substantially common depth, and forming an etch stop layer in the alignment mark.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: September 23, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Mahjoub A. Abdelgadir, Stephen C. Kuehne, Alvaro Maury, Scott F. Shive
  • Patent number: 6548906
    Abstract: The present invention provides a method of manufacturing an interconnect structure. The method may include forming a nucleation layer, including a first metal, over a barrier layer and within an opening formed in a dielectric layer, forming an intermediate layer, including a second metal such as titanium nitride, over the nucleation layer and within the opening, and forming a plug portion layer, including the first metal, over the intermediate layer and within the opening. The first metal may be tungsten and the second metal may be a titanium nitride layer.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: April 15, 2003
    Assignee: Agere Systems Inc.
    Inventors: Nace Layadi, Alvaro Maury
  • Publication number: 20030038369
    Abstract: The present invention provides a method of manufacturing an interconnect structure. The method may include forming a nucleation layer, including a first metal, over a barrier layer and within an opening formed in a dielectric layer, forming an intermediate layer, including a second metal such as titanium nitride, over the nucleation layer and within the opening, and forming a plug portion layer, including the first metal, over the intermediate layer and within the opening. The first metal may be tungsten and the second metal may be a titanium nitride layer.
    Type: Application
    Filed: August 22, 2001
    Publication date: February 27, 2003
    Inventors: Nace Layadi, Alvaro Maury