Patents by Inventor Alwin J. Tsao
Alwin J. Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9397164Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.Type: GrantFiled: November 18, 2015Date of Patent: July 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
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Patent number: 9379176Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.Type: GrantFiled: October 22, 2015Date of Patent: June 28, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Stephen Keith Heinrich-Barna, Douglas P. Verret, Alwin J. Tsao
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Publication number: 20160079364Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.Type: ApplicationFiled: November 18, 2015Publication date: March 17, 2016Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
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Publication number: 20160056227Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.Type: ApplicationFiled: October 22, 2015Publication date: February 25, 2016Inventors: Stephen Keith Heinrich-Barna, Douglas P. Verret, Alwin J. Tsao
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Patent number: 9245755Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.Type: GrantFiled: December 18, 2014Date of Patent: January 26, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
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Publication number: 20150349046Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.Type: ApplicationFiled: May 27, 2014Publication date: December 3, 2015Inventors: Stephen Keith Heinrich-Barna, Douglas P. Verret, Alwin J. Tsao
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Patent number: 9202859Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.Type: GrantFiled: May 27, 2014Date of Patent: December 1, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Stephen Keith Heinrich-Barna, Douglas P. Verret, Alwin J. Tsao
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Publication number: 20150187760Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.Type: ApplicationFiled: December 18, 2014Publication date: July 2, 2015Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
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Patent number: 7274046Abstract: The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].Type: GrantFiled: June 2, 2005Date of Patent: September 25, 2007Assignee: Texas Instruments IncorporatedInventors: Lahir Shaik Adam, Eddie H. Breashears, Alwin J. Tsao
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Patent number: 7141480Abstract: The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].Type: GrantFiled: March 26, 2004Date of Patent: November 28, 2006Assignee: Texas Instruments IncorporatedInventors: Lahir Shaik Adam, Eddie H. Breashears, Alwin J. Tsao
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Patent number: 6693357Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.Type: GrantFiled: March 13, 2003Date of Patent: February 17, 2004Assignee: Texas Instruments IncorporatedInventors: Christopher Lyle Borst, Alwin J. Tsao, Bobby David Strong, Noel Russell
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Patent number: 6333238Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.Type: GrantFiled: December 6, 2000Date of Patent: December 25, 2001Assignee: Texas Instruments IncorporatedInventors: Greg C. Baldwin, Alwin J. Tsao
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Publication number: 20010000122Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2) , a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.Type: ApplicationFiled: December 6, 2000Publication date: April 5, 2001Inventors: Greg C. Baldwin, Alwin J. Tsao
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Patent number: 6211769Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.Type: GrantFiled: December 8, 1998Date of Patent: April 3, 2001Assignee: Texas Instruments IncorporatedInventors: Greg C. Baldwin, Alwin J. Tsao
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Patent number: 6162728Abstract: A method for forming copper interconnect lines using a damascene process. After the formation of the copper seed layer (112) and prior to the formation of the copper layer (120), a pattern (114) is formed to block the formation of the copper in non-interconnect areas. The copper layer (120) is then formed and the pattern (114) is removed. The exposed seed layer (112) and any barrier layers (110) thereunder are removed.Type: GrantFiled: September 27, 1999Date of Patent: December 19, 2000Assignee: Texas Instruments IncorporatedInventors: Alwin J. Tsao, Paul M. Gillespie
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Patent number: 6143594Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.Type: GrantFiled: January 26, 2000Date of Patent: November 7, 2000Assignee: Texas Instruments IncorporatedInventors: Alwin J. Tsao, Vikas I. Gupta, Gregory C. Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost
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Patent number: 6137144Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.Type: GrantFiled: March 30, 1999Date of Patent: October 24, 2000Assignee: Texas Instruments IncorporatedInventors: Alwin J. Tsao, Vikas I. Gupta, Gregory C. Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost