Abstract: Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.

Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.

Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.

Abstract: The disclosed approaches involve executing simulator-parallel processes that correspond to states of a finite state machine representation of a circuit design. Execution of each simulator-parallel process is initiated in response to an event generated by another one of the simulator-parallel processes. A data access transaction of the circuit design is simulated by calling a first function of a wrapper from a first process of the simulator-parallel processes. The first process waits for an estimated number of simulation clock cycles. The estimated number of simulation clock cycles represents an actual time period required to complete an actual data access transaction.

Abstract: Approaches for protection of HLL simulation models in a circuit design having unprotected high-level language (HLL) program code and first metadata of a shared library of executable simulation models that are based on sensitive HLL simulation models. A design tool determines a first storage location of the shared library based on the first metadata and compiles the unprotected HLL program code into an executable object. The design tool links the executable object with the library of executable simulation models from the first storage location and then simulates the circuit design by executing the executable object and loading the executable simulation models in response to initiation by the executable object.

Abstract: Diagnosing applications that use hardware acceleration can include emulating, using a processor, a kernel designated for hardware acceleration by executing a device program binary implementing a register transfer level simulator for the kernel. The device program binary is executed in coordination with a host binary and a static circuitry binary. During the emulation, error conditions may be detected using diagnostic program code of the static circuitry binary. The error conditions may relate to memory access violations or kernel deadlocks. A notification of error conditions may be output.

Abstract: Implementing a kernel as circuitry in an integrated circuit can include determining, using a processor, memory access operations and work operations from kernel program code and generating, using the processor, a circuit design from the kernel program code. The circuit design implements a circuit architecture having a memory access circuit configured to perform the memory access operations and an execution circuit configured to perform the work operations concurrently with the memory access operations.

Abstract: Using pin planning for core sources includes identifying, using a processor, a first pin configuration and a second pin configuration for a core source of a behavioral description of a circuit design. The second pin configuration is generated by a pin planning operation. The first pin configuration of the core source can be compared with the second pin configuration of the core source using a processor. Responsive to detecting a difference between the first pin configuration and the second pin configuration, the core source can be automatically update, using the processor, based upon the second pin configuration.

Abstract: Emulating a heterogeneous application having a kernel designated for hardware acceleration may include compiling, using a processor, host program code into a host binary configured to execute in a first process of a computing system and generating, using the processor, a device program binary implementing a register transfer level simulator using the kernel. The device program binary may be configured to execute in a second, different process of the computing system. A high level programming language model of static circuitry of a programmable integrated circuit that couples to a circuit implementation of the kernel may be compiled into a static circuitry binary. The static circuitry binary may be used by the register transfer level simulator during emulation.

Abstract: A circuit design is created in a computer memory in response to user input to a computer processor. The circuit design has a static portion. A virtual socket is instantiated in the circuit design in response to user input, and one or more reconfigurable modules are instantiated in the virtual socket in response to user input. The static portion of the circuit design is coupled to the one or more reconfigurable modules, and configuration data are generated from the circuit design. The configuration data include a configuration bitstream corresponding to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more reconfigurable modules.

Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

Abstract: A method is provided for generation of a circuit design. A set of design assistance rules is retrieved from a database. Each design assistance rule in the set includes a list of design objects to which the design assistance rule applies, a set of criteria to be satisfied by the circuit design before the design assistance rule may be applied, a set of configuration options, and an executable script configured to perform an automated configuration of the circuit design. In response to a change in the circuit design, applicable design assistance rules are determined based on the corresponding sets of criteria. In response to determining that one or more design assistance rules are applicable, data indicating that the one or more design assistance rules are available is output. In response to input that selects a design assistance rule the executable script corresponding to the selected design assistance rule is executed.

Abstract: A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock cycle boundaries determined during a simulation session.

Abstract: Method and apparatus for providing self-implementing hardware-software libraries is described. One aspect of the invention relates to designing an embedded system for an integrated circuit. A hardware platform is defined. A software platform is defined having a plurality of software components, including a library. Hardware component dependency data associated with the library is identified. At least one hardware component is added to the hardware platform in response to the hardware component dependency data.

Abstract: A variety of CLB architectures enable the efficient implementation of sum-of-products functions in a PLD. Output signals from each lookup table (LUT) in a CLB are routed directly to a dedicated OR structure, bypassing other logic typically included in a CLB. Thus, the LUTs can be programmed to implement AND functions, with the AND function results being ORed together in the dedicated OR structure. In this manner, a fast and efficient sum-of-products output signal is provided. In some embodiments, the dedicated OR structure includes programmable means for selectively combining the signals from the LUTs. In these embodiments, LUTs with output signals that are ignored by the dedicated OR structure can be used to implement unrelated logic.