Patents by Inventor Amit Vasudevan

Amit Vasudevan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240352475
    Abstract: The present disclosure provides methods of producing heme proteins in transgenic plants, plant tissues, or plant cells, as well as describing the expression of these heme proteins in seeds. Also, the present disclosure provides transgenic plants expressing the heme proteins, myoglobin and hemoglobin, by introducing and integrating the recombinant DNA constructs into the host genetic material of the subject plants. The specific combination of regulatory elements disclosed herein allows for high heme protein expression level in seeds.
    Type: Application
    Filed: April 26, 2024
    Publication date: October 24, 2024
    Inventors: Gaston PALADINI, Martin SALINAS, Amit DHINGRA, Henk HOOGENKAMP, Bruce Williamson BENAVIDES, Maria Laura MALVINO, Balaji VASUDEVAN
  • Publication number: 20240346132
    Abstract: Disclosed herein is a method for defining a model of a trusted IoT security gateway architecture based on a microhypervisor, wherein evaluation of the model provides a guarantee that the correct security protections are applied to each IoT device's network traffic at all times, including when under attack. The models defined in accordance with the method disclosed herein are used to verify security gateway architectures that provide robust trust properties to a broad range of legacy hardware platforms utilizing existing software with a reasonable performance overhead.
    Type: Application
    Filed: July 13, 2022
    Publication date: October 17, 2024
    Applicant: CARNEGIE MELLON UNIVERSITY
    Inventors: Amit Vasudevan, Matthew McCormack, Vyas Sekar
  • Publication number: 20240340336
    Abstract: A technique may include receiving, by a management service a plurality of instance configurations from a client device. The technique may then include receiving, by the management service, information identifying a launch request for a compute instance. The technique may include determining, by the management service, one or more candidate shapes for the compute instance based at least in part on the plurality of instance configurations. The technique may include selecting, by the management service and from the one or more candidate shapes, a launch shape for the compute instance and launching the compute instance using the launch shape. The technique may then include providing, the client device access to the compute instance, launched based on the launch shape.
    Type: Application
    Filed: April 7, 2023
    Publication date: October 10, 2024
    Applicant: Oracle International Corporation
    Inventors: Jonathan Luke Herman, Art Plata, Joshua Potter, John Matthew Mullins, Nathan Cook, Nathan Turner, Tianyi Wei, Amit Vasudevan, Haifeng Ren, Harsh Verma, Jiafeng Yang, John David Martinez, Daniel Stuart Goldfein, Mahima Tomer
  • Publication number: 20240311454
    Abstract: A system includes a memory and a processor coupled to the memory. The processor receives a first user credential associated with a first user and authorizes an avatar of the first user to enter a virtual environment. The processor receives a first selection of an experience theme and a second selection of at least one product type from the selected experience theme. The processor determines a first data file that provides a first benefit count to the first user when a first amount of data objects is transferred from a first data file of the first user to a second data file. The processor indicates to the first user that the first data file provides the first benefit count to the first user, receives a command to obtain the first data file, and initiates a registration process to register the first user to obtain the first data file.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 19, 2024
    Inventors: Anushka Pandey, Rajat Singla, Siva Kesava, Praveen Kumar Parsa, Murugan Vasudevan, Krithika Viswanathan, Amit Mishra
  • Patent number: 12093367
    Abstract: Disclosed herein is a system architecture that structures commodity heterogeneous interconnected computing platforms around universal object abstractions, which are a fundamental system abstraction and building block that provides practical and provable end-to-end guarantees of security, correctness, and timeliness for the platform.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: September 17, 2024
    Assignee: Carnegie Mellon University
    Inventor: Amit Vasudevan
  • Publication number: 20240289432
    Abstract: Disclosed herein is a system architecture that structures commodity heterogeneous interconnected computing platforms around universal object abstractions, which are a fundamental system abstraction and building block that provides practical and provable end-to-end guarantees of security, correctness, and timeliness for the platform.
    Type: Application
    Filed: April 1, 2024
    Publication date: August 29, 2024
    Applicant: CARNEGIE MELLON UNIVERSITY
    Inventor: Amit Vasudevan
  • Publication number: 20240267736
    Abstract: Disclosed herein is a system and method implementing a trusted IoT security gateway architecture, based on a microhypervisor, that provides a guarantee that the correct security protections are applied to each IoT device's network traffic at all times, including when under attack. The disclosed architecture provides robust trust properties to a broad range of legacy hardware platforms utilizing existing software with a reasonable performance overhead.
    Type: Application
    Filed: June 22, 2022
    Publication date: August 8, 2024
    Applicant: CARNEGIE MELLON UNIVERSITY
    Inventors: Amit VASUDEVAN, Matthew McCORMACK, Vyas SEKAR
  • Publication number: 20220350876
    Abstract: Disclosed herein is a system architecture that structures commodity heterogeneous interconnected computing platforms around universal object abstractions, which are a fundamental system abstraction and building block that provides practical and provable end-to-end guarantees of security, correctness, and timeliness for the platform.
    Type: Application
    Filed: March 1, 2022
    Publication date: November 3, 2022
    Applicant: Carnegie Mellon University
    Inventor: Amit Vasudevan
  • Patent number: 9367701
    Abstract: A method for operating a computing system with a trusted processor include generating a secret cryptographic key based on a physically unclonable function in at least one hardware component in the trusted processor, generating a first public key and first private key using first secret cryptographic key, and executing instruction code corresponding to a first software program. The method further includes generating output data with the trusted processor during execution of the first software program, generating encrypted data corresponding to the output data using the first public key for at least a portion of the encryption, generating a signature of the encrypted data, and transmitting with an input/output (I/O) interface operatively connected to the trusted processor the encrypted data and the signature for storage in an untrusted memory.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 14, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Jorge Guajardo Merchan, Emmanuel Kwame Owusu, Jonathan McCarrell McCune, James Duran Newsome, Jr., Amit Vasudevan, Adrian Perrig
  • Publication number: 20140258736
    Abstract: A method for operating a computing system with a trusted processor include generating a secret cryptographic key based on a physically unclonable function in at least one hardware component in the trusted processor, generating a first public key and first private key using first secret cryptographic key, and executing instruction code corresponding to a first software program. The method further includes generating output data with the trusted processor during execution of the first software program, generating encrypted data corresponding to the output data using the first public key for at least a portion of the encryption, generating a signature of the encrypted data, and transmitting with an input/output (I/O) interface operatively connected to the trusted processor the encrypted data and the signature for storage in an untrusted memory.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 11, 2014
    Applicant: Robert Bosch GmbH
    Inventors: Jorge Guajardo Merchan, Emmanuel Kwame Owusu, Jonathan McCarrell McCune, James Duran Newsome, JR., Amit Vasudevan, Adrian Perrig
  • Patent number: 8627414
    Abstract: A computer including a processor and a verification device. The processor in the computer performs the steps of authenticating a secure connection between a hypervisor and the verification device, measuring the identity of at least a portion of a select guest before the select guest executes any instruction, and sending a measurement of the identity of the select guest to the verification device. The verification device compares the policy stored in the verification device with the measurement of the select guest received by the verification device. The steps of authenticating, measuring, sending, and comparing are performed after receiving a signal indicative of a request to execute the select guest and without rebooting the computer.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: January 7, 2014
    Assignee: Carnegie Mellon University
    Inventors: Jonathan M. McCune, Adrian M. Perrig, Anupam Datta, Virgil Dorin Gligor, Yanlin Li, Bryan Jeffrey Parno, Amit Vasudevan, Ning Qu
  • Publication number: 20080127114
    Abstract: A framework and method for creating malware analysis tools for dynamic and stealth coarse- and fine-grained malware analysis is provided. In one embodiment a method stalls the execution of a desired code on any form of access to memory or other devices. This can be used to monitor the behavior of the malware with respect to the system at a high level. Upon identification of a high level access, another method can be employed in order to decompose a desired range of code into its individual instructions as they execute thereby revealing the inner structure of the malware as it executes. Since the framework does not employ any processor debugging features, and its methods are self-resilient and completely invisible to the executing code, malware that employ any form of anti-debugging and/or anti-analysis strategy including using framework methods can be easily and effectively analyzed.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 29, 2008
    Inventor: Amit Vasudevan