Patents by Inventor Amitava Chatterjee

Amitava Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9245755
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Patent number: 9231054
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • Publication number: 20150380551
    Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventor: Amitava Chatterjee
  • Patent number: 9202912
    Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: December 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shaoping Tang, Amitava Chatterjee, Imran Mahmood Khan, Kaiping Liu
  • Publication number: 20150294967
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: June 25, 2015
    Publication date: October 15, 2015
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Publication number: 20150249040
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Publication number: 20150249088
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 9099523
    Abstract: A semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the buried layer. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the buried layer.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 4, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Publication number: 20150187938
    Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.
    Type: Application
    Filed: December 19, 2014
    Publication date: July 2, 2015
    Inventors: Shaoping TANG, Amitava CHATTERJEE, Imran Mahmood KHAN, Kaiping LIU
  • Publication number: 20150187760
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Application
    Filed: December 18, 2014
    Publication date: July 2, 2015
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Patent number: 9064726
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 23, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 9059032
    Abstract: An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: June 16, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Theodore W. Houston, Puneet Kohli, Amitava Chatterjee
  • Patent number: 8975135
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiping Liu, Amitava Chatterjee, Imran Mahmood Khan
  • Patent number: 8933510
    Abstract: An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 13, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Amitava Chatterjee, Imran Khan
  • Patent number: 8860147
    Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Howard Tigelaar, Victor Sutcliffe
  • Publication number: 20140295631
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Inventors: Kaiping LIU, Amitava CHATTERJEE, Imran Mahmood KHAN
  • Publication number: 20140252485
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Publication number: 20140227859
    Abstract: Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.
    Type: Application
    Filed: March 20, 2014
    Publication date: August 14, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Kamel BENAISSA, Amitava CHATTERJEE
  • Patent number: 8779550
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: July 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiping Liu, Amitava Chatterjee, Imran Mahmood Khan
  • Publication number: 20140183655
    Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.
    Type: Application
    Filed: December 19, 2013
    Publication date: July 3, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Derek W. ROBINSON, Amitava CHATTERJEE