Patents by Inventor Amitava Chatterjee

Amitava Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7112497
    Abstract: The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: September 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Vivian Liu, Amitava Chatterjee
  • Publication number: 20060205169
    Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).
    Type: Application
    Filed: March 8, 2005
    Publication date: September 14, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Jong Yoon, Shirin Siddiqui, Amitava Chatterjee, Brian Goodlin, Karen Kirmse
  • Patent number: 7098099
    Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: August 29, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Brian E. Hornung, Jong Yoon, Deborah J. Riley, Amitava Chatterjee
  • Publication number: 20060189066
    Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.
    Type: Application
    Filed: February 24, 2005
    Publication date: August 24, 2006
    Applicant: Texas Instruments, Incorporated
    Inventors: Brian Hornung, Jong Yoon, Deborah Riley, Amitava Chatterjee
  • Patent number: 7045436
    Abstract: A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Alwin Tsao, Manuel Quevedo-Lopez, Jong Yoon, Shaoping Tang
  • Patent number: 7045410
    Abstract: A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Amitava Chatterjee
  • Patent number: 7039888
    Abstract: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: May 2, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Philipp Steinmann, Amitava Chatterjee, Doug Weiser, Roland Bucksch
  • Publication number: 20060084230
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Application
    Filed: December 7, 2005
    Publication date: April 20, 2006
  • Patent number: 7029967
    Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: April 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Song Zhao, Sue E. Crank, Amitava Chatterjee, Kaiping Liu, Jiong-Ping Lu, Donald S. Miles, Duofeng Yue, Lance S. Robertson
  • Patent number: 7018888
    Abstract: The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: March 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Brian E. Goodlin, Amitava Chatterjee, Shirin Siddiqui, Jong S. Yoon
  • Publication number: 20060027895
    Abstract: A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall deposit and etch and then source/drain pattern and implant for nMOS and pMOS. The method includes the steps of forming emitter and collector contacts by implants used in source/drain regions; forming an emitter that includes implants done in core pMOS during core pMOS LDD extender and pocket implant steps and while the collector omits the core pMOS LDD extender and pocket implants; forming a base region below the emitter and collector contacts by the n-well region with said base region going laterally from emitter to collector being the n-well and including pocket implants; and forming base contact by said n-well region and by implants used in nMOS source/drain regions.
    Type: Application
    Filed: September 30, 2005
    Publication date: February 9, 2006
    Inventor: Amitava Chatterjee
  • Publication number: 20060024910
    Abstract: A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).
    Type: Application
    Filed: July 27, 2004
    Publication date: February 2, 2006
    Inventors: Amitava Chatterjee, Alwin Tsao, Manuel Quevedo-Lopez, Jong Yoon, Shaoping Tang
  • Publication number: 20060024909
    Abstract: A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively provided to a portion of the active region (303) proximate the isolation region (305) to create a threshold voltage compensation region (318). After the compensation region (318) is created, the hard mask layer (304, 308) is patterned (218) to create a patterned hard mask. The patterned hard mask is then used in forming (222) a trench (323) in the isolation region (305) near the compensation region (318), and the trench (323) is then filled (224) with a dielectric material (338).
    Type: Application
    Filed: July 27, 2004
    Publication date: February 2, 2006
    Inventors: Manoj Mehrotra, Amitava Chatterjee
  • Publication number: 20060024911
    Abstract: A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).
    Type: Application
    Filed: July 27, 2004
    Publication date: February 2, 2006
    Inventors: Freidoon Mehrad, Amitava Chatterjee
  • Publication number: 20060024872
    Abstract: The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).
    Type: Application
    Filed: July 30, 2004
    Publication date: February 2, 2006
    Applicant: Texas Instruments, Incorporated
    Inventors: Brian Goodlin, Amitava Chatterjee, Shirin Siddiqui, Jong Yoon
  • Publication number: 20060019478
    Abstract: A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
    Type: Application
    Filed: July 21, 2004
    Publication date: January 26, 2006
    Inventors: Song Zhao, Sue Crank, Amitava Chatterjee, Kaiping Liu, Jiong-Ping Lu, Donald Miles, Duofeng Yue, Lance Robertson
  • Patent number: 6987039
    Abstract: A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall deposit and etch and then source/drain pattern and implant for nMOS and pMOS. The method includes the steps of forming emitter and collector contacts by implants used in source/drain regions; forming an emitter that includes implants done in core pMOS during core pMOS LDD extender and pocket implant steps and while the collector omits the core pMOS LDD extender and pocket implants; forming a base region below the emitter and collector contacts by the n-well region with said base region going laterally from emitter to collector being the n-well and including pocket implants; and forming base contact by said n-well region and by implants used in nMOS source/drain regions.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: January 17, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Amitava Chatterjee
  • Publication number: 20050287751
    Abstract: The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths.
    Type: Application
    Filed: June 25, 2004
    Publication date: December 29, 2005
    Inventors: Freidoon Mehrad, Vivian Liu, Amitava Chatterjee
  • Publication number: 20050149887
    Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
    Type: Application
    Filed: November 19, 2004
    Publication date: July 7, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, David Scott, Theodore Houston, Song Zhao, Shaoping Tang, Zhiqiang Wu
  • Publication number: 20050145949
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Application
    Filed: February 8, 2005
    Publication date: July 7, 2005