Abstract: A touch controller of a computing device can adjust various modes of operation of a touch panel in order to conserve resources on the device. The touch controller can dynamically adjust a rate at which touch sensors are scanned, or can scan touch sensors for the display panel using a different mode than for a single input button or other such element. The touch controller can also operate in a low power mode while the device is in standby, and then activate a high power mode of operation upon detecting an input such as a double tap. The touch controller can also alternate between low and high power modes of operation based at least in part upon a current application executing on the device.

Abstract: A system and method is provided for making highly accurate data propagation delay measurements in a serializer/deserializer (SERDES) integrated circuit. The invention detects a selected special character when the special character is present at the input of a transmit data path of the SERDES integrated circuit. The invention also detects the special character when the special character appears at the output of the transmit data path. The invention then counts the number of clock cycles during which the selected character was in the transmit data path. This provides the data propagation delay of the special character through the transmit data path. The invention also makes data propagation delay measurements for a receive data path of a SERDES integrated circuit.

Abstract: Error-free data transfer between mesochronous clock domains can be accomplished by writing data to and reading data from a plurality of data storage elements in coordinated fashion. Write operations are controlled by execution of a state sequence synchronously with the source clock domain, and read operations are controlled by execution of the same state sequence synchronously with the destination clock domain. The states respectively correspond to the data storage elements, and the read and write executions of the state sequence do not simultaneously assume the same state.

Abstract: A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a bit period to create errors at a relatively high bit error rate. This is accomplished by intentionally introducing an interpolator offset in a phase position of a data clock signal. The test control unit generates a first bit error rate and then subsequently generates a second bit error rate. The test control unit then uses the values of the first and second bit error rates to extrapolate a value of bit error rate for the clock and data recovery circuit that corresponds to a zero value of interpolator offset.

Abstract: A system and method is disclosed for providing a clock and data recovery circuit with a self test capability. A test control unit is provided that causes the clock and data recovery circuit to continuously alter a phase of an interpolated clock signal. A user selects a preselected bit pattern that causes the digital control circuitry of the clock and data recovery circuit to advance or retard the phase of the interpolated clock signal. The test control unit compares the advanced or retarded phase of the interpolated clock signal with a reference clock signal to determine a frequency difference between the two clock signals. The test control unit uses the frequency difference to determine the test status of the clock and data recovery circuit.

Abstract: A system and method is provided for making highly accurate data propagation delay measurements in a serializer/deserializer (SERDES) integrated circuit. The invention detects a selected special character when the special character is present at the input of a transmit data path of the SERDES integrated circuit. The invention also detects the special character when the special character appears at the output of the transmit data path. The invention then counts the number of clock cycles during which the selected character was in the transmit data path. This provides the data propagation delay of the special character through the transmit data path. The invention also makes data propagation delay measurements for a receive data path of a SERDES integrated circuit.

Abstract: A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.